Enable pin control for lpc11u6x soc by selecting CONFIG_PINCTRL=y.
At this time no drivers are ported.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pin control for lpc11u6x i2c driver, and remove pinmux usage from
board level DTS files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
convert lpc11u6x syscon clock driver to pin control, and remove all
pinmux usage from driver and syscon dts node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update pin control driver for lpc11u6x. This SOC does not have a HAL,
so fsl_clock is not available. It also lacks a slew-rate field in the
IOCON register, so this property must be optional.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
switch gpio driver to use pio nodes to configure pin control settings,
and stop using pinmux driver within gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Improve the power domain logging by making the log level configurable
and boosting the log level of the messages printed when the domain turns
on and off.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The following HALs contain code that makes use of Zephyr headers, so
they have been updated with the <zephyr/...> prefix:
- Altera
- NXP
- STM32
- TI
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adjust get_mem_region to not return region when address == end
as there will be nothing to read there. Also, a subsequent region
may have that address as a start address and would be a more appropriate
selection.
Signed-off-by: Mark Holden <mholden@fb.com>
Now we define PROPERTY_OUTPUT_FORMAT (which is used for
binutils) only for ARCv3 32 bit. Let's define it for all
ARC elf formats instead of relying on default values.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Provide required compiler/assembler options for building with mwdt
toolchain for ARCv3 64 bit.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Use correct gfrc version in nsim args for mdb_hs6x_smp board.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Add nSIM-based (simulator) boards with
* nsim_hs5x - single core ARCv3 HS5x 32 bit CPU
* nsim_hs5x_smp - SMP, two core ARCv3 HS5x 32 bit CPU
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
K_THREAD_STACK_DEFINE is not correct in a header file as it may conflict
with K_THREAD_STACK_DEFINE usage in the source file.
Signed-off-by: Keith Packard <keithp@keithp.com>
Adding support for the GIC_V1 to the dc_dw USB driver
to be used by Cyclone V SoC FPGA Development Kit
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
Cyclone V SoC FPGA supports 128Byte FIFO for UART communication,
this modification adds a feature to use 128byte FIFO serial UART
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
LCD display is connected to the I2C bus SoC bus in the development kit,
this sample guides the user on how to use the LCD display with I2C commands
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
Add a runner to "flash" and "debug" Cyclone V SoC FPGA Development Kit
the runner is based on OpenOCD and GDB
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
The audio stream receive callback now contains a
recv_info struct, which contain crucial information
such as timestamps and packet validity.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The values represent an enum, and it makes sense for the
enum values to follow the enum type name, so an
_DIR_ infix was added to the values.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The PAC_TYPE_UNUSED would be breaking
enum rules, as it is setting and comparing
a value outside the enum range.
Instead we check if the `dir` field has been
set to SINK or SOURCE.
The reason why this still works, is that
we memset the struct unicast_client_pac
causing `dir` to become 0. This still
does not really follow the rules of enums, but
it is the best we can do without adding another
value to determine if a struct unicast_client_pac
is unused or not, without adding another value to
public enum struct.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Many functions and struct fields had the directory/type
value, but named in different ways and stored in different ways.
This change updates all uses of it to use the same name
and type.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The enum bt_audio_pac_type does not fully
represent the what the value is used for.
The typical use of it is not for just published
audio capabilities (PAC), but rather describes the
type, or direction, of audio endpoints.
For the unicast client, the type/direction is
relative to the unicast server.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The unicast_client_ep_init took a ID value that was
always 0. Moved the initialization to the value to
the function, instead of an argument. The value
is only used for the unicast server, so it can
probably be removed from the endpoint
struct for unicast clients only. To be optimized later.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The endpoint.type field was unused as it was
always LOCAL for the unicast server and always
REMOTE for the unicast client, and the few places
where we actually checked it, we already had a
check for acl->role which gave the same value.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Verifies ISOAL functionality for VS RX data path by implementing weak
function ll_data_path_sink_create, and implementing sink callbacks.
Test verifies construction of sink and checks that SDUs are emitted in
VS sink implementation.
Test relies on the Nordic synchronous receiver implementation, and is
compiled under CONFIG_BT_CTLR_ISO_VENDOR_DATA_PATH, which is enabled in
the project file.
Signed-off-by: Morten Priess <mtpr@oticon.com>
Since implementation of clock source selection in consumer device drivers
could be achieved without usage of a clock-names property and no
example of usage is provided up to now, remove this property from existing
examples.
Additionally, make it clear in stm32 clock control binding that it is
driver's responsibility to correctly access clock source information
and use it as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a test section to enable device clock source selection testing.
Test targets I2C1 device which supports clock source selection
on all SOCs using this driver except L1
Initial test done on wb target.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move stm32_common tests to stm32_common_core before adding new folder
for device source selection tests.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Similarly to what was done on U5 and H7 clock_control drivers, enable
device clock source selection.
This is done by:
-providing implementation for clock_control_configure().
-updating clock_control_get_rate() to support various possible clock
sources (SYSCLK, PLLCLK, LSE, LSI, HSI, HSE).
-providing enable_clock() to verify requested clock source exists and
is enabled.
-adding LSI and LSE device tree based initialization to
set_up_fixed_clock_sources().
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clock sources bindings on F0/F3/G0/G4/L0/L1/L4/WB/WL series.
Due to inconsistencies, some common bindings are now split:
F1 -> F0/F1/F3
L4 -> L4/G4/WB
Update .dtsi files when required
In a first step, allowed sources are limited to already supported
clocks: LSI/LSE/HSI/HSE/MSI/PCLK/PLLCLK/SYSCLK
Support for other clocks such as HSI48, SAIXCLK, ... is left for a
next step.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename and factorize clock source bindings accessors by moving them
in common header file stm32_clock_control and remove them from
include/dt-bindings/clock/stm32XY_clock.h files
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz
fix PLLM can't be higher than 1.
Fix PLL1-NQR in consequence.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
