Even one liner if () should have get { ... }
Change-Id: I7f9d8d74398286e97549bed050e29d4d175e1b02
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit removes unnecessary CONFIG_SYS_POWER_DEEP_SLEEP protection
in shim drivers as QMSI 1.4 has introduced empty context save/restore
functions that can be called in Quark D2000, therefore keeping common
code at the shim driver level for Quark SE and D2000.
Change-Id: Ia2a466327f999668c6511c0193014e9151bff6ae
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Enable arc to access the spi controller on I/O fabric.
There are two spi controllers on quark se SoC. One is attached
to the I/O fabric and the other one is in the sensor system.
X86 cpu is only able to access the spi controller on the I/O
fabric and the access is supported by existing code. HW allows
arc to access both controllers. But, the existing code only
gives arc access to the controller in the sensor sub-system.
Let's grant arc the access to the controller on I/O fabric as
well by the following changes.
1. Add spi_qmsi.c into arc compilation.
2. Use the already defined macros to choose interrupt numbers
and do interrupt unmasking automatically based on the
compilation targets.
3. Add new symbols in Kconfig including driver names for both
controllers
Jira: ZEP-1190
Change-Id: I40a5d423d4b7986a897834d1a3831938005eda6f
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Device sync APIs are actually wrappers for semaphores.
Let's replace them with semaphores.
Jira: ZEP-1411
Change-Id: I02c7cba21d21ff9288e452121e3b7ebb7d251bb4
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Add function return value check. This was caught by
Coverity.
Coverity-CID: 157124
Change-Id: I93b23325d657dc787300908b9117b6976617fdba
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit updates the spi_qmsi driver by removing the temporary Zephyr
save/restore context implementation and using the new QMSI APIs.
Jira: ZEP-997
Change-Id: I70c6838025253d13d6ebe690ec90dfc1b18bfcea
Signed-off-by: JuanX Solano Menacho <juanx.solano.menacho@intel.com>
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:
- QM_SCSS_INT is renamed to QM_INTERRUPT_ROUTER;
- every member of QM_INTERRUPT_ROUTER was renamed as well;
- QM_IRQ_* renamed too, mostly added _INT at the end;
- some isr functions were renamed to keep their names consistent;
- build for x86 needs to define QM_LAKEMONT, as QM_SENSOR was for ARC.
Change-Id: I459029ca0d373f6c831e2bb8ebd52402a55994d1
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Make pointers to struct config_info const in prepration for a const
config_info.
Change-Id: I1ca9e999840a6ad81dc369b56b1da554f3c1cb49
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Update the power sample and drivers with the new device driver power
management API using the existing logic
Jira: ZEP-954
Change-Id: Idd94232e458767635973e94e9fc673c01612c1e2
Signed-off-by: Amir Kaplan <amir.kaplan@intel.com>
This patch implements suspend/resume routines which
preserve SPI master 0 and 1 context in SYS_PM_DEEP_SLEEP.
The following parameters are suspended/resumed:
- All non-sticky RW registers for the SPI device which
are not related to a transfer.
- The SPI MASK registers (interrupt routing register).
The suspend/resume functionality is implemented in
the QMSI shim layer as a fast and temporary solution,
it will be removed and migrated to QMSI later.
Change-Id: Ib60317ca41013a3e794820e9c3ef34f35d108209
Signed-off-by: Dragan Cvetic <dragan.cvetic@intel.com>
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Drivers that implement power management should use the preferred
device_pm_ops method instead.
Change-Id: I337722b1e06afe8508b5c84c00c3542571232e07
Signed-off-by: Iván Briano <ivan.briano@intel.com>
This will allow the driver to be fiber and task safe
Change-Id: I916d4ad67ab6f51f41f3d1136c105e4d1445de48
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Use the same Kconfig infrastructure and options for all SPI drivers.
Jira: ZEP-294
Change-Id: I7097bf3d2e1040fcec166761a9342bff707de4dd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not have priority per IP, use one config instead.
Change-Id: Ieb2923d4749a294e2a1c677d47d56a14cee3f36d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch replaces all occurences of the macro DEV_USED by -EBUSY
at the driver level. So this patch touch the files under drivers/,
include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I21eb3ffe9bdfde98593dcf63c50a8bdcd376e49e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_INVALID_CONF by
-EINVAL at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: Idae0d5af8dd780416977c9261a5fb6188c3aab64
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_FAIL by -EIO
at the driver level. So this patch touch the files under drivers/,
include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I0594ab5dbe667e074c250129e7c13ce512ac940f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_OK by the actual
value 0 at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I69980ecb9755f2fb026de5668ae9c21a4ae62d1e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
There's no reason to require callers to cast their data to uint8_t *
when the data might e.g. originate in a packed struct or some other
data type. Instead, be nice to callers and let them use any pointer
they want. Additionally, declare the TX buffer as a const pointer so
unnecessary typecasts aren't needed for that either (if the data
originates in a const location).
Change-Id: I1482ca4e350b5a7fbda6871ed9f54f255af3aa9e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This patch fixes the QMSI SPI shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in spi_qmsi_init() because the macro QM_SPI_MST_1
and the function qm_spi_master_1_isr are not defined in QMSI headers
from Quark D2000.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: Ic6e2f7f5a2c3f350ddf360b23ffab6b812948572
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
There are situations when the transfer starts before we have the time to
enable the CS line, so to be sure, we active it before even attempting
to start the transfer.
This fixes an CC2520 driver initialization issue using the QMSI SPI driver.
Change-Id: Ib9b324b77260ac537f714376c8056b1543e7e3b3
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Because of the necessity of using a GPIO pin as Chip Select, we need to
set the initialization priority of the SPI driver so it occurs after the
GPIO driver.
Change-Id: I02d675d8267ee07b267155a3806be85fbf57378c
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
There are cases that it is needed to use a GPIO pin as chip
select (frames would be too long, for example), so using a GPIO pin as
chip select to keep the line active while the transfer is ongoing is the
usual solution.
This implements that solution for the QMSI shim driver.
Change-Id: Ia6b8f0f17161e20f87ad3def1468fe0abea65fdc
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This driver uses the QMSI library and mostly translates calls from the
Zephyr API to QMSI ones.
This driver conflicts with the native driver implemenation. In order to
enable it, you must set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="PATH_TO_QMSI"
CONFIG_SPI_QMSI=y
CONFIG_SPI_QMSI_PORT_0=y
CONFIG_SPI_QMSI_PORT_1=y
Missing:
- Support for using a GPIO pin as Chip Select;
Change-Id: I0d8eca88a2a803b6b3604f396f874313fe90753c
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
