Provides tool set to be used by device drivers in order to be able
to configure device signals.
This does not involve the implementation of a dedicated pinctrl
driver. In this regard, this is equivalent to implementation used
for treatment of current pinmux.c files.
Since STM32F1 uses a different GPIO configuration scheme, its
support is exlcuded for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We need the same logic for each SOC, instead of copypasting
things just put this in a common file. This approach still
leaves the door open for custom memory layouts if desired.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
STM32L151xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, and amount of interrupts (57, see STM32Cube).
Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
Adds imx rt support.
Allows n-number of can interfaces based on device-tree.
Adds a "common" irq name.
Added CAN bus pins and dts for 1060 and 1064 EVK.
Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
The standard and static MMU regions (_code, _rodata and _data) are
already covering all the available SRAM region and all the needed
sections. Remove the overlapping SRAM region.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
We only need to offset the start of the non-secure image
by 0x400, if TFM is built with BL2 support. In this case
we use the ROM_START_OFFSET Kconfig switch and set to
0x400. This instructs the linker to offset the beginning
of the ROM section by 0x400. In other words, we do not need
to statically move the start of the image by 0x400. This
fixes an issue that prevents from running Zephyr + TFM
without BL2 on Musca B1.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We only need to offset the start of the non-secure image
by 0x400, if TFM is built with BL2 support. In this case
we use the ROM_START_OFFSET Kconfig switch and set to
0x400. This instructs the linker to offset the beginning
of the ROM section by 0x400. In other words, we do not need
to statically move the start of the image by 0x400. This
fixes an issue that prevents from running Zephyr + TFM
without BL2 on MPS2 AN521.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When we wake-up of deep sleep power state, we want to disable it.
Otherwise, when the cpu will go next to idle mode during a
SYS_POWER_STATE_ACTIVE, it will go into deep sleep mode
instead of a sleep mode.
fixes: #26896
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
This STM32 serie redefines function relocate_vector_table()
It should take into account features:
SW_VECTOR_RELAY and SW_VECTOR_RELAY_CLIENT
fixes#28289
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Select the controller feature support for data length and LE 2M PHY
based on the SoC hardware capabilities instead of relying on SoC
family.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
0.5 Mhz with 100 ticks per sec leaves 5000 cycles per tick,
which broke some tests that assumed more work within 1 tick.
Set to 1 Mhz: balance multi-core simulation speed and tick duration.
Fixes#27943
Signed-off-by: Ruud Derwig <Ruud.Derwig@synopsys.com>
The commit aac9e2c5e3
("device: Revise how initialization status is being handled") highlights
an initialization priority issue between the clock and pinmux device.
Since this commit Zephyr is not booting anymore on LPC11U6x MCUs. The
clock driver gets a NULL pointer when calling device_get_binding() to
retrieve the pinmux device. It is because the pinmux device is not
initialized yet due to a lesser priority.
This patch fixes this issue by ensuring that Zephyr initializes the
pinmux device before the clock device.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Employ the nRF-specific timing calculations framework
(based on TIMER peripheral) only if the DWT is not present
on the SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
nRF51 TIMER2 periperhal does not have the 32-bit
bitmode, so we need to fallback to the bitmode 16.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add timing functions and APIs. This is now used with some of the tests
we have for performance and metrics and will be used whereever timing
informations are needed, for example for tracing, profiling and other
operations where timing info is critical.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The dmamux requires HEAP size definition, so that k_malloc
is valid. The HEAP size config is defined in the common for
any stm32 soc instead of specific to dma Kconfig
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add devicetree support to specify bias-pull-up, bias-pull-down, and
drive-open-drain for pin configuration.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixed 'line length exceeds 80 columns' warning by shortening the clock
controller device name from NPCX_CLOCK_CONTROL_NAME to
NPCX_CLK_CTRL_NAME.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The general DMA driver doesn't use kmalloc anymore so it doesn't
need a memory pool. The DMAMUX_SMT32 driver still uses kmalloc,
so move the HEAP_MEM_POOL_SIZE config under DMAMUX_STM32.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Typically we have ARC core configurations where Fast IRQs (FIRQ) are
enabled together with multiple register files and those we have covered
by testing. But FIRQ & single register bank we only happen to have on
the older EMSK v2.2.it might be a good idea to add a similar
configuration to nSIM "boards" so that we keep it tested regularly.
nsim_em7d_v22 configuration is similar with em_staterkit_em7d_v22,
both configed with FIRQ & single register bank.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Assuming we stay on default Power Scale 1,
overdrive is required when System Core Clock frequency is higher
than 180MHz.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Most drivers make use of the HW semaphore (see `stm32_gpio.c`), but the
HSEM clock isn't currently setup on the MCU side. This means we rely on
the MPU to enable this clock, which is an unsafe bet: the OS running on
the MPU may not have support for HSEM, or it might enter sleep state,
which will disable the clock. As a consequence, firmwares loaded from
the MPU running this OS will block on the first `z_stm32_hsem_lock()`
call.
As it is required to run anything on the MCU core, we shouldn't assume
the HSEM clock is already active when booting and enable it in the SoC
init, the same way it is done for the STM32H7.
Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Replace npcx register base address type, uint32_t, with uintptr_t.
It is easier to know what type of base address and for linear
addresses treated as integral values.
This CL also modified IS_BIT_SET() macro function to fit MISRA code
guidelines.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add gpio support for Nuvoton NPCX series. This CL includes:
1. Add GPIO device tree declarations.
2. Introduce wui_maps property in yaml file to present relationship
between Wake-Up
Input (WUI) and 8 IOs belong to the device.
3. Zephyr GPIO api implementation.
4. GPIO callback functions implementation with MIWU api functions.
5. Overlay file for gpio basic tests
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The device Multi-Input Wake-Up Unit (MIWU) supports the embedded
controller (EC) to exit 'Sleep' or 'Deep Sleep' power state which allows
chip has better power consumption. Also, it provides signal conditioning
such as 'Level' and 'Edge' trigger type and grouping of external
interrupt sources of NVIC. The NPCX series has three identical MIWU
modules: MIWU0, MIWU1, MIWU2. Together, they support a total of over 140
internal and/or external wake-up sources.
In this CL, we use device tree files to present the relationship bewteen
MIWU and the other devices in different npcx series. For npcx7 series,
it include:
1. npcx7-miwus-int-map.dtsi: it presents relationship between MIWU group
and NVIC interrupt in npcx7. Please notice it isn't 1-to-1 mapping.
2. npcx7-miwus-wui-map.dtsi: it presents relationship between input of
MIWU and its source device such as gpio, timer, eSPI VWs and so on.
This CL also includes:
1. Add MIWU device tree declarations.
2. MIWU api function declarations and implementation to configure signal
conditions and callback function mechanism. They can be be classified
into two types. One is for GPIO which connects original gpio callback
implemetation and the other is for generic devices such as timer,
eSPI, and so on.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
To indicate that the CLOCK and POWER peripherals are present in those
SoCs, thus the corresponding nrfx drivers can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
