Currently there is no way to distinguish between a caller
explicitly asking for a semaphore with a limit that
happens to be `UINT_MAX` and a semaphore that just
has a limit "as large as possible".
Add `K_SEM_MAX_LIMIT`, currently defined to `UINT_MAX`, and akin
to `K_FOREVER` versus just passing some very large wait time.
In addition, the `k_sem_*` APIs were type-confused, where
the internal data structure was `uint32_t`, but the APIs took
and returned `unsigned int`. This changes the underlying data
structure to also use `unsigned int`, as changing the APIs
would be a (potentially) breaking change.
These changes are backwards-compatible, but it is strongly suggested
to take a quick scan for `k_sem_init` and `K_SEM_DEFINE` calls with
`UINT_MAX` (or `UINT32_MAX`) and replace them with `K_SEM_MAX_LIMIT`
where appropriate.
Signed-off-by: James Harris <james.harris@intel.com>
This fixes the logic in erase_sector() for clearing the previous
sector number. The logic was reversed, clearing bits it should not
clear and keeping previous bits of the sector number. In practice this
does not seem to have had any effect on the current functionality, but
it will start to matter later if e.g. flash interrupts are enabled.
Signed-off-by: Göran Weinholt <goran.weinholt@endian.se>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
nRF52840, nRF52810, nRF52811 and nRF52805 are affected by anomaly 242.
This patch introduces workaround for this anomaly as follow:
Power-fail comparator is disabled before any attempt to erase or write.
Either erase or write is not proceed if EVENT_POFWARN is
already asserted.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Introduce support for situation when synchronization back-end
aborts operation before it is done. synchronization API will
transfer operation return code to the driver shim back.
Additionally:
FLASH_OP_ONGOING value was switched to be positive in order to
not been mislead with a negative error code.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
This commit fixes sporadic kernel panics when writing big data chunks
to the flash. (data bus errors)
Reference manual:
If an erase operation in Flash memory also concerns data in the data
or instruction cache, you have to make sure that these data are
rewritten before they are accessed during code execution.
If this cannot be done safely, it is recommended to flush the caches
by setting the DCRST and ICRST bits in the Flash access control
register (FLASH_ACR).
Signed-off-by: Alexander Wachter <alexander.wachter@leica-geosystems.com>
Some format strings were causing warnings.
As elsewhere in this file, offset is type-casted (or not,
depending on compiler) to long int, and then %ld is used in
format string.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
Added selection of MPU_ALLOW_FLASH_WRITE.
Using a flash driver while MPU is enable without
this option on doesn't make sense at all.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Older LPC platforms use Flash IAP with a command style firmware command.
Tested on LPC54114 platform.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The flash shell can work with any flash driver instance, not just the
one chosen by zephyr,flash-controller. It's helpful for the flash shell
to use this instance by default, but not required. We can switch
instances at runtime with the "flash set_device" command.
Fix the flash shell so it can build when there isn't a chosen
zephyr,flash-controller available.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Introduces a new flash driver for the FlexSPI peripheral on i.MX RT
SoCs. The hardware provides a flexible sequence engine (LUT) that
supports various types of external devices, including serial NOR flash,
serial NAND flash, HyperBus (HyperFlash/HyperRAM), and FPGAs. It
supports up to four connected devices in single/dual/quad/octal modes
and provides memory-mapped read/write access to these devices through
the AHB bus.
The driver implementation consists of a shared controller for each
FlexSPI peripheral instance, and protocol-specific device drivers for
each external device. The controller provides a private interface for
multiple devices to access the FlexSPI peripheral registers. FlexSPI
devices provide the public flash driver interface to applications or
subsystems like storage or flash file systems; they also provide
protocol-specific LUT sequences to the controller.
Currently the only device type supported is QSPI NOR flash, but other
types like HyperFlash will be added later.
XIP is not yet supported, as this requires additional work to relocate
code to RAM and managing interrupts.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactor slightly so we can read SFDP tables with this driver. Note
that the SFDP read command requires long frame mode transfers as data
exceeds 8 bytes.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
QSPI doesn't have a different length expectation than normal SPI, so
introducing a new name for an existing name is unnecessary. Also
replace the constant with the actual buffer size where appropriate, in
somebody changes the the buffer definition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Kconfig allowed selecting any bit in the status register as the QE
bit, and defaulted it to 6. Devices need not require a QE bit at all,
and where JESD216 defines QE bit location the only place in first SR
byte that it can be is bit 6. Further, the code unconditionally wrote
the value 0x40 without respecting configuration of other bits. Some
of those bits control write protection of block-protected areas and
should not be changed.
Remove the Kconfig, instead using the jedec,jesd216-controlled
devicetree property. Allow the driver to recognize whether or not
setting the bit is required, and when it is only use bit 6. Only
update if the setting does not match the configuration.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The interface used to send commands supports only a command followed
by 8 bytes of data transfer. Reject attempts to do more, as the
result will be a successful transfer of only the first 8 bytes.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Not all special commands require that a write-enable be issued first.
Allow the caller to decide.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW16 provides information on mechanisms to enter and exit 4-Byte
address modes, returning the device to reset state, and how to
manipulate the values in the first status register.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW15 provides information on entry and exit from QSPI modes. In
particular, it specifies whether and how the status register must be
updated for this feature.
Add a JESD216 devicetree property for the Quad Enable Requirements
value.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
In order to ease reuse on other series, set DMA as optional
and use IT if no DMA channel is specified in the qspi node.
Tested on disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for DMA based STM32 QSPI NOR flash controller.
Driver configures both NOR flash and also QSPI hardware block.
Reuses existing jesd216 library.
QSPI hardware block handling is done through the use of Cube HAL API.
This requires the use of HAL interface also for DMA besides zephyr
DMA driver.
Zephyr DMA driver is used only for IRQ routing while HAL driver
handles the IP block. To achieve this it is required to:
-Configure both Cube and Zephyr drivers at init.
-Inform Zephyr driver that current channel handling will be done
by another instance and only a limited configuration should be done.
For this last part, a unused parameter is overridden in order to
transmit the information.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
When flash is Dualbank and flash size is lower than 512K,
then there is a discontinuity between bank1 and bank2.
Also take into account bank swap capability.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Flash size is specified in bits by SFDP and devicetree, but the stored
flash size is in bytes. Correct the divisor.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
off_t can be 32-bit or 64-bit depending on the platform. STM32 flash
addresses are always 32-bit so it's safe to use long here.
Signed-off-by: Martin Jäger <martin@libre.solar>
Convert soc nios2 qspi to DEVICE_DEFINE instead of DEVICE_AND_API_INIT
so we can deprecate DEVICE_AND_API_INIT in the future.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Flash controller support is not yet ready on M4 core.
Remove the chosen declaration to make it clear.
Additionally, generate a build error if this driver is compiled
on M4 core.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fixes#29831: Implements flash driver for stm32h7 devices.
The driver is independant from the other stm32 families (flash_stm32.c),
only the header interface is (mainly) common.
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
Add weak function to check flash configuration.
On stm32g4: single bank configuration not supported
when dual bank capable.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Remove hardcode bank1 page limit (128) which is not always valid
(not valid for soc stm32g474rct)
Manage bank1/2 discontinuity when flash is Dualbank and
flash size is lower than 512K.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When flash is Dualbank and flash size is lower than 512K,
then there is a discontinuity between bank1 and bank2.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move users that are DEVICE_DT_DECLARE(DT_DRV_INST(n, ...)) to
DEVICE_DT_INST_DECLARE(n, ...) and similar for DEVICE_DT_DEFINE.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixes#29831: Implements flash driver for stm32h7 devices.
The driver is independant from the other stm32 families (flash_stm32.c),
only the header interface is (mainly) common.
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
The exclusive bound for parameter headers needs to be incremented as
the nph parameter is not the number of parameter headers: 0 means one
header.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Use the devicetree node as the source of object name and other
information used when defining the device structure.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The driver was using CONFIG_SRAM_BASE_ADDRESS as the value used to
recognize whether source buffer is in RAM. This label provide the
base address of the image SRAM, and not the base of actual HW SRAM.
This patch uses nrfx_is_in_ram() instead.
fixes#29467
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
The at45 and nor spi flash drivers needs flash layout to work.
Probably tested were conducted with SoC that already selects
the FLASH_HAS_PAGE_LAYOUT for internal flash drivers. This add
the missing dependency.
Fixes#28094.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Clearing the PSIZE bits in the FLASH CR should not invert the mask
defined in stm32f4xx_hal_flash.h (#define CR_PSIZE_MASK 0xFFFFFCFFU)
Signed-off-by: Justin Brederveld <jmbrederveld@gmail.com>
