Do not override OUI of the local MAC address in the devicetree.
Simplify the mac address assignment conditions. Each interface has
its own function. Code duplication will be eliminated with the
use of DT_INST_FOREACH_STATUS_OKAY in a later commit to completely
remove duplicated code.
The 3 possible MAC address assignment (local, random and unique)
are covered and have been tested.
Signed-off-by: Armand Ciejak <armand@riedonetworks.com>
This fixes wrong value for i.MX RT.
This is one less hard-coded value in eth_N_context structures.
Signed-off-by: Armand Ciejak <armand@riedonetworks.com>
This allows setting the MAC address at run time.
Signed-off-by: Antoine Zen-Ruffinen <antoine@riedonetworks.com>
Signed-off-by: Armand Ciejak <armand@riedonetworks.com>
The PLL Q divisor does not exist on stm32g0X0 variants. It should only
be configured for g0X1 variants.
Signed-off-by: Eric Hay <EHay@sierrawireless.com>
CheckRfFrequency was not assigned correctly to the Radio. This lead
to the system hang when the loramac library tries to call a relevant
Radio method when processing a join-accept message
Signed-off-by: Kuba Sanak <contact@kuba.fyi>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
For preparing the radio drivers (specifically SX1276) for LoRaWAN
support, let's add missing function definitions and callbacks required
by the stack.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Since TimerIrqHandler() API does SPI transactions, it is not advised to
call from an IRQ context. Hence, offload it to a work queue.
Reported-by: Andreas Sandberg <andreas@sandberg.pp.se>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
The loramac-node library definition will also be created by
'subsys/lorawan' for the LoRaWAN support. Hence, just add the source
files if the previous declaration of the library is found else create
a new one.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Now that Zephyr names have been made short and nice the need of these
helpers is less justified.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add const modifier for hal instances, clock devices pointer, and module
base address in npcx drivers to prevent driver functions change them
unexpectedly.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
In npcx7 series, there're 8 Pulse Width Modulator (PWM) modules and each
one support generating a single 16-bit PWM output. A 16-bit clock
prescaler (PRSCn) and a 16-bit counter (CTRn) determine the cycle time,
the minimal possible pulse width, and the duty-cycle steps.
Beside introducing pwm driver for Nuvoton NPCX series, this CL also
includes:
1. Add PWM device tree declarations.
2. Zephyr PWM api implementation.
3. Add aliases in npcx7m6fb_evb board device tree file for supporting
samples/basic/blinky_pwm application and pwm test suites
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Make sure remap is disabled when not requested.
This should have no impact on current cases but is important
when dynamic pin configuration will be used.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
There are cases where the socket would not be closed.
offload_put function will now always close the socket
properly.
Remove error log messages as they are redundant.
on_cmd_sock_error_code handles printing errors.
Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
This part of common code for ADC drivers, the adc_context_enable_timer()
function, was still converting sampling interval values to milliseconds
(the only option available at the time this code has been created) when
setting up the kernel timer, consequently limiting the maximum sampling
frequency to 1000 samples per second. This patch switches the routine
to specifying the interval in microseconds, to remove this limitation.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This emulator supports enable functionality to start up the device and
read a few samples. It connects itself to any BMI160 device it finds in
the device tree. The SPI emulation controller driver is used to direct
SPI messages from the BMI160 driver to the BMI160 emulator.
Add a few more definitions to the header file, as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an emulation controller which routes SPI traffic to an attached
emulator. Only one emulator is supported per bus at present, since
chip-selction functionality is not present.
This allows drivers for SPI peripherals to be tested on systems that
don't have that peripheral attached, with the emulator handling the SPI
traffic.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present register access is a mix of constants and open-coded values
in the driver. Add a few more constants to clean this up.
Signed-off-by: Simon Glass <sjg@chromium.org>
If HW flow control is enabled, then modem_context framework won't drain
UART FIFO blindly, but will stop when there is no more space in RX
ring_buf. This prevents data loss by "pausing" incoming data on hardware
level.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
If HW flow control is enabled, then modem_context framework won't drain
UART FIFO blindly, but will stop when there is no more space in RX
ring_buf. This prevents data loss by "pausing" incoming data on hardware
level.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
So far all received bytes over UART where blindly drained and pushed to
ring_buf. This approach is okay for UART devices without configured HW
flow control, as it basically decouples data processing from ISR handler
and gives more time before data overrun. However when HW flow control
is enabled, such behavior somehow suppresses UART flow control
advantage, because data can overrun when pushing to ring_buf.
Allow drivers utilizing modem_context framework to pass information
about whether HW flow control is enabled or not. If it is enabled, then
read data from UART FIFO to the point when RX ring_buf is totally filled
and follow such situation by disabling RX interrupt. Incoming data will
be paused on HW level, so there is lots of time for RX thread to process
ring_buf content. Reenable RX interrupts after all data in ring_buf is
processed, so that number of context switches is kept at minimum level.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This API allows to drop use of preallocated isr_buf. Most importantly as
a result RAM usage is reduced for each driver utilizing modem_context
framework. Additionally there is less copying done in ISR context, as
data is direcly read from UART FIFO to ring_buf.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Restore the flash write proectction after disabling it for
flash write and erase shell commands.
Signed-off-by: Ievgenii Meshcheriakov <ievgenii.meshcheriakov@nordicsemi.no>
Flash drivers are free to re-enable write protection after a write or
erase operation is complete. Therefore write protection has to be
disabled before any such operation.
Signed-off-by: Ievgenii Meshcheriakov <ievgenii.meshcheriakov@nordicsemi.no>
The second argument of this foonction is a bool, so passing 0 and 1
is incorrect.
Coccinelle script:
@@
expression e;
@@
flash_write_protection_set(e,
(
- 0
+ false
|
- 1
+ true
)
)
Signed-off-by: Ievgenii Meshcheriakov <ievgenii.meshcheriakov@nordicsemi.no>
1. clock: move the call for MSI hardware auto calibration enabling
before the control of MSI enable to ensure its execution in all
cases.
2. counter: add call for MSI hardware auto calibration enabling after
the LSE enabling and after possible backup domain reset that may
clear MSIPLLEN.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
Described in ES096 2.14.7,
F101X8/B, F102X8/B, and F103X8/B
might not be able to enter i2c master mode on power-up.
Force reset help to mitigate this issue.
Signed-off-by: Yiyu Zhu <smallzzy@outlook.com>
Replace all calls to the assert macro that comes from libc by calls to
__ASSERT_NO_MSG(). This is usefull as the former might be different
depending on the libc used and the later can be customized to reduce
flash footprint.
Signed-off-by: Xavier Chapron <xavier.chapron@stimio.fr>
This adapts the driver to changes in the LiteX CSR accessors API
introduced in the previous commit.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This change allows to use SSD1306 based displays to be used on the
SPI bus as well.
Adding SPI shield.
Tested on SSD1306 and SSD1309 based displays using I2C.
Tested on SSD1309 based display using SPI.
Signed-off-by: Marco Peter <marco@peter-net.ch>
This change removes the interleaving control
frames.
Additionally all I2C accesses are centralized in
one single function.
Signed-off-by: Marco Peter <marco@peter-net.ch>
This CL adds more comments for each macro functions used for device tree
file for better explanations. It also changes all hex values in soc.c to
lower case.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL contains the drivers of NPCX Host Sub-Modules that serve as an
interface between the Host and Core domains. For most of them, the Host
can configure these modules via eSPI(Peripheral Channel)/LPC by
accessing 'Configuration and Control register Set' which IO base address
is 0x4E as default. And the interrupts in core domain help handling any
events from host side.
In this commit, we introduced six host sub-modules. It includes:
1. Keyboard and Mouse Controller (KBC) interface.
2. Power Management (PM) channels.
3. Shared Memory mechanism (SHM).
4. Core Access to Host Modules (C2H).
5. Mobile System Wake-Up functions (MSWC).
6. Serial Port (Legacy UART)
The tasks in application layer such as 8042, ACPI and host command can
cooperation with this driver by connecting api or callback functions.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
In npcx7 series, all of them support the Intel Enhanced Serial
Peripheral Interface (eSPI) Revision 1.0. This specification provides a
path for migrating host sub-devices via LPC to a lower pin count, higher
bandwidth bus. In addition to Host communication via the peripheral
channel, it provides virtual wires support, out-of-band communication,
and device mastering option over the Chipset SPI flash.
Becisdes introducing eSPI device in npcx7, this CL also includes:
1. Add eSPI device tree declarations.
2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI
Virtual-Wire signals, eSPI registers, and wake-up input sources.
3. Zephyr eSPI api implementation.
4, Add OOB (Out of Band tunneled SMBus) support.
5. Add configuration files for eSPI test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Fixed build error in in eSPI socketpair test suite since wrong function
name for eSPI flash channel api.
This CL also fixed [-Werror=unused-function] warning by adding inline
attribute in case someone includes "espi_utils.h" and doesn't call
espi_manage_callback() function.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
