Of course IPM drivers now provide their device instance. There are 2
drivers using IPM callbacks as well, so they get the imp device instance
pointer now through the callback.
Fixes#26923
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It was already using uart_irq_callback_user_data_set below, now it also
uses uart_irq_callback_user_data_t as callback type, so let's normalize
the callbacks.
Fixes#26923
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This patch adds adds an EEPROM driver supporting the on-chip EEPROM
found on NXP LPC11U6X MCUs. Note that this driver is only a wrapper
relying entirely on the IAP (In-Application Programming) EEPROM
commands.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This patch adds a pinmux driver allowing to configure the IOCON (I/O
control) registers found on the LPC11U6x MCUs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Flexcomm's SPI SSEL (or CS) will be held until frame end.
FIFOWR[EOT] (kSPI_FrameAssert enum) is the register not set.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Per the nrf9160 datasheet, UARTE must be disabled prior to configuring
PSEL.TXD, PSEL.RXD, PSEL.CTS, and/or PSEL.RTS. This also ensures that
any prior running code, such as a bootloader, which leaves the UART
enabled will not prevent the Zephyr application from changing the
configuration.
Make a similar change also to the uart_nrf_uart.c driver for the
nRF5 series.
Fixes 27080
Signed-off-by: Pete Skeggs <peter.skeggs@nordicsemi.no>
Need to call PINT_Init to initialize the block
before using it. This fixes the issue seen on
RT600 with the button example
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
- Use common clock names to avoid build error.
- Use GPIO_PortInit() to do reset/clock initialization. Only clock
enable is not adequate for RT600.
- Update to support differences between IOCON and IOPCTL modules
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
There are multiple CID errors all based on the test of
'socket > ESWIFI_OFFLOAD_MAX_SOCKETS'. The test needs to
be '>=' in all cases.
Fixes: #27138Fixes: #27139Fixes: #27140Fixes: #27141Fixes: #27142Fixes: #27143
Signed-off-by: David Leach <david.leach@nxp.com>
By fixing the issue: #21819 in the shell, it is no longer needed
to keep a workaround, which allows prompting i2c bus name.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordisemi.no>
When CONFIG_POSIX_API is set in lieu of CONFIG_NET_SOCKETS_POSIX_NAMES,
some macros such as POLLIN, POLLOUT and MSG_PEEK are undefined, and
the appropriate posix headers need to be included to access those.
Signed-off-by: Vincent Wan <vwan@ti.com>
Adds native_posix hw counter model and the counter driver.
Functionality is needed by software which is tested
on native_posix and has dependency on counter.
Hardware model was developed similarly to HW timer model.
The counter driver wraps HW counter functions and exposes
basic functionalities: starting, stopping, setting and cancelling
single channel alarms.
Code was tested against: tests/drivers/counter/counter_basic_api.
Signed-off-by: Filip Zajdel <filip.zajdel@nordicsemi.no>
Add HSE,HSI,CSI,PLL as system clock options.
Also add correct configuration of the PLL.
New sysclk options:
- HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y
- HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y
- CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y
Existing sysclk options:
- PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
PLL clock options:
- More PLL source clocks:
Existing:
1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
New:
2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y
- PLL vco input range is auto-calculated based on PLL DIVM1
-> Example for sysclock 96MHz generated with PLL from HSI
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h
instead to setup the correct latency.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
eSPI slave driver should only indicate that a channel is ready
after the eSPI master has enabled said channel.
However, this indication is incorrectly sent during eSPI reset
even before channel renegotiation starts.
Perform only channel-specific interrupts enabling inside
initialization functions.
Send Channel ready ack only after channel negotiation is received.
Add missing callbacks for channel events to notify client driver.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Update stm32 ethernet driver to get basic boot configuration from
device tree.
So far information are:
- Label
- Base address
- IRQ number and prio
- Clock settings
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add 64bit source_address/dest_address fields support.
This is needed in situation where DMA controller is capable
of handling more than 32bit source and destination addresses.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Fix compilation warnings when CONFIG_NET_SOCKETS_OFFLOAD enabled
warning: passing argument 5 of '__eswifi_socket_new' makes pointer
from integer without a cast [-Wint-conversion]
395 | idx = __eswifi_socket_new(eswifi, family, type, proto, 0x50CE);
| ^~~~~~
| |
| int
eswifi.h:137:21: note: expected 'void *' but argument is of type 'int'
137 | int proto, void *context);
| ~~~~~~^~~~~~~
In function 'eswifi_socket_bind':
warning: comparison between pointer and integer
461 | if ((addrlen == NULL) || (addr == NULL) ||
|
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
use common log module across all eswifi sources, which allows
to compile with CONFIG_NET_SOCKETS_OFFLOAD.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
It is useful to show sensor channels for a battery in cohesive block as
it is easier to read. Add a 'battery' command to handle this. It only
supports a single battery, relying on the device-tree alias to select
it.
uart:~$ battery
Temp: 23.55 C
V: 4.31 V
V-desired: 4.40 V
I: 574 mA (CHG)
I-desired: 2000 mA
Charging: Not Allowed
Charge: 100 %
V-design: 3.86 V
Remaining: 6764 mA
Cap-full: 6764 mA
Design: 6910 mA
Time full: 0h:00
Time empty: 0h:00
Signed-off-by: Simon Glass <sjg@chromium.org>
The EEPROM device doesn't mutate the source data it's given, so update
the API signature to reflect this fact.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
It can happen that the command '>' is received between
modem_cmd_send_nolock and modem_cmd_handler_update_cmds. Since the
command handler for '>' is not set, sem_tx_ready will not be given
and _sock_send will timeout. Make sure the command handlers are set
before the send by also passing them to modem_cmd_send_nolock.
Signed-off-by: Tobias Svehagen <tobias.svehagen@gmail.com>
Add support for the NXP KE1xF SoC to the eDMA driver. The KE1xF supports
m2m DMA transfers from sources 60 to 63.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
add DTCM caching management in KConfig for stm32h7
add NOCACHE_MEMORY support for stm32h7 M7 CPU series
add HAL_RCC_EX support for stm32h7 series
implemented stm32h7 support within stm32 eth driver
Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
added changes that apply to other than stm32h7 series
and prepares stm32h7 series integration:
eth_tx/eth_rx: changed type of total_len
added necessary defines for
tx_desc and own flag extractions
added read_eth_phy_register() function
and corresponding defines
added ETH_DMA_MEM and CACHE defines
following memory buffers declarations moved out of
its ifdef preprocessor macro:
dma_rx_desc_tab, dma_tx_desc_tab,
dma_rx_buffer, dma_tx_buffer
added hal_ret stm32 HAL status checks
Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
Added extra asserts to write function of SDL display driver to check if
write is within bounds.
Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
IPv6 support was not fully implemented in the driver and was disabled.
This commit completes the implementation and enables it when
configured.
Signed-off-by: Vincent Wan <vwan@ti.com>
After switching nSIM to 16550 UART model & driver there is no users
for ARC-NSIM UART. So remove it entirely.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Adapted driver to clock_control changes (usage of onoff manager).
Since timer is permanenty requesting the clock, it is using API
dedicated for that: z_nrf_clock_control_lf_on().
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Updated nrf clock control driver to use onoff service for managing
multiple users.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
FLASH_TYPEERASE_PAGES is null and doesn't represent a bit in the
register, thus this instruction has no effect.
It must be replaced by FLASH_CR_PER which is the bit that should
be cleared.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Added function read_non_aligned that reads data under
non-aligned flash addres to non-aligned read buffer of any size.
Signed-off-by: Mateusz Syc <Mateusz.Syc@nordicsemi.no>
Add support for wsen-itds 3-axis accel sensor, provides acceleration,
temperature data reading and supports configuring of output data rate,
operating mode and scale.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
This gets a little complicated as the driver could be
using PCI-E MMIO, MMIO specified by DTS, or I/O ports.
This driver doesn't use struct uart_device_config any
more.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Good example of the NAMED variants of the MMIO macros, since
an existing inheritance mechanism already took the first-member
slot of the dev_data/config structs.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fairly straightforward example of how to deal with PCIe.
The code considers whether a particular instance is PCIe
or not on a per-instance basis, so DEVICE_MMIO_ROM is not
conditionally defined.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A hack was required for the loapic code due to the address
range not being in DTS. A bug was filed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The ethernet driver no longer continues to try to initialize
itself if PCIe probing fails.
This device is always PCIe so we don't need to reserve ROM MMIO
storage.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fix typo in logged Kconfig option name that is missing in used
configuration. This one was mostly problematic for developers wanting to
find such option in source tree using grep - NET_SOCKET_OFFLOAD was not
found in Kconfig files.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
With this refactoring of pcie directory, RC drivers are placed under
host/ directory, EP drivers are placed under endpoint/ directory and
they are completely independent of each other.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
The antenna control GPIO was incorrectly initialized to active. This
is unnecessary since the HAL will activate the antenna switch when the
chip enters an active state.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
The new sx1276 pin configuration helpers can be used by the sx126x
driver as well. Move them to sx126xx_common.{c,h} to facilitate reuse.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Fixed AF for USART 6 on PC6/PC7 PG8/PG9/PG12/PG13/PG14/PG15
All RTS/CTS/RX/TX pins now have correct AF7 instead of wrong AF8.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
The wdt CLEAR register is a write synchronized register.
To avoid bus stall, check the status of SYNCBUSY before
accessing the register.
Use SYNCBUSY register for SAM E.
If the wdt is syncing, return -EAGAIN to avoid bus stall.
Signed-off-by: Steven Slupsky <sslupsky@gmail.com>
Add support to STM IIS2DH the ultra-low-power highperformance
three-axis linear accelerometer.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add option to concatenate i2c transfers. If concatenation buffer size is
provided then transfers will be concatenated as long as there is space
left in buffer.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Added a build-time assert to check if heap memory configuration to
make sure that it can accomodate RPMsg queue allocations.
Ref: NCSDK-5479
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
In case of control register lock, driver should return the error
immediately. Otherwise, error is later overwritten by
'rc = flash_stm32_wait_flash_idle(dev);'
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
ep_idx is common used designator for endpoint index,
rename ep_num to ep_idx in usb_dc_sam0 driver.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
This commit adds a dependency on the TRNG resource in the TI Power
module, prevents the system policy from entering standby when TRNG is
active, and adds support for device PM.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Abort I2C transfers through the MCUX HAL if a transfer fails to avoid
deadlock in the driver/HAL.
Fixes#25098
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Reset gpio is configured during driver initialization. There is no
reason to do it repeat that process later, so replace
gpio_pin_configure() with gpio_pin_set().
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Introduce sx1276_configure_pin() helper macro, which hides lots of
boilerplate preprocessor and C code. Doing so allows to uncover
inconsistent gpio initialization flow and prevent such in future. Also
add error log whenever gpio_pin_configure() fails.
It seems like output of gpio_pin_configure() for several
gpios (antenna_enable, rfi_enable, rfo_enable) was assigned to variable,
but its values was never checked. Return value from gpio_pin_configure()
of tcxo_power gpio was even not catched. The only output gpio
configuration that was handled properly was actually reset gpio.
Fix that inconsistent behavior by always checking return value of
sx1276_configure_pin().
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Fix flash operation timeout due to incorrect use of
secondary ticker to abort any radio in use. Ticker id 0
is reserved for split controller's pipeline preempt timeout.
Using the same ticker id caused the secondary ticker to
not be started if controller is using the same ticker id
for pipeline preempt timeout.
Fixes#26333.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Suppress -Wchar-subscripts warnings when building with Newlib, by
casting isdigit() parameter to unsigned char.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
LPC55xxx SoCs don't allow reading erased areas, the flash memory
controller (FMC) will trigger an ECC error for that area. To prevent
reading unwritten areas the low level FMC command of margin checking is
used, this will fail if the area to be read is not correctly written
(margin_check) or area is erased (blank_check).
In the case of an erased page, we return dummy data so the application
can program that area.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
In case of dualcore, STM32H7, STM32W and STM32MP1,
protect concurrent register write access with HSEM.
Done for following drivers:
clock_control, counter, flash, gpio, interrupt_controller
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The generic SPI GPIO chip select support now respects devicetree flags
for signal active level. This pass DT information to driver instance to
ensure proper behavior.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Unit tests were failing to build because random header was included by
kernel_includes.h. The problem is that rand32.h includes a generated
file that is either not generated or not included when building unit
tests. Also, it is better to limit the scope of this file to where it is
used.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Since the i2c init structure is moved from config_info to the stack,
this change requires 12 bytes more stack during driver initialization.
This fixes#25255
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
wifi-reset-gpios flags were not respected so far. This means that
setting reset as active low (which is required in most cases for ESP
modules/chips) was done inside esp driver with inverted logic. Use dts
flags instead, so "active low" property is configured the same way as
for other drivers (i.e. in device-tree instead of driver).
This change also allows to configure reset as active high, in case where
ESP's nRST signal is somehow inverted on the board (behaving as RST
signal instead).
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
PCI devices on 64 bit systems can be mapped anywhere, not just in the
lower 4G of memory. Remove pointer size assumptions.
Also this removes the use of a struct uart_device_config to store the
(runtime) BAR address. That struct has other stuff in it, and the
only thing we need is the single MMIO address. It's also REALLY
confusing to have two "devconf" fields in the device storing values of
the same struct type, some fields of which are used from one of them
but some from the other!
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The PCI API was originally limited to 32 bit addresses. Even though
it had code to skip over the high word in 64 bit BAR entries, it
refused to use it and returned a 32 bit value. Some devices in the
wild have default mappings from the firmware for devices above 4G.
Also remove the "iobar" API. It's dead code, we don't call it and we
don't test it. IO space BAR entries are a legacy feature from way,
way back in PCI history (I genuinely have never heard of a real device
that uses them!). And there's no difference in format between one of
these and a 32 bit "memory" BAR anyway, someone who actually had this
requirement could just use the existing API without worry.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When checking the absolute value of cycles set to the comparator
use the MAX_CYCLES instead of MAX_TICKS.
The commit changes function names and comments to make it clear
where ticks (system ticks) and where RTC cycles are used.
Fixes#26701
Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
It is annoying to read just a single word at a time. Update this
command to print any amount of data. This uses byte format at present.
We could perhaps support something like:
flash read.8
flash read.16
flash read.32
to chose the size.
Example output (with line breaks to keep within git-style limit):
$ flash read FLASH_CTRL 0 20
00000000: 20 25 00 20 1d 26 00 08 69 68 00 08 45 26 00 08
| %. .&.. ih..E&..|
00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|........ ........|
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver blocks on a semaphore to receive notification when an
operation is complete, so requires CONFIG_MULTITHREADING=y.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Since commit 5963ebaf33
("drivers: spi: CS configuration through devicetree")
the SPI GPIO CS flags are obtained from DT,
but the patch series has missed the necessary changes
for the ieee802154_dw1000 driver and decawave_dwm1001_dev board.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
K_FOREVER/INT_MAX number of ticks needs delay cycles value of
maximum order and exceeds 'int32' range.
The typecast to 'int32' results in wrongly evaluating the value
as less than 'MIN_DELAY' and chooses 'MIN_DELAY' over the actual
delay cycles.
Cap the 'MAX_TICKS' to INT32_MAX.
fixes: #26632
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Make sure to retry at least once after the timeout elapses. Sample the
current time before starting the i2c transaction, and only give up if
the polling occurred after the timeout.
The timeout exists to allow the eeprom time to complete a write, during
which time it will nack transactions (at24) or the status register will
report busy (at25). If a transaction fails legitimately, but the 1ms
sleep overshoots the timeout expiration, we will not try again, which
fails to give the part the full grace period before declaring failure.
This is likely to happen in the last 1ms interval but also possible if
the eeprom thread is preempted. It is possible to only try once and give
up if the sleep lasts longer than the timeout, which fails to give the
part an adequate period to complete the write.
Waiting until the current time is after (not equal to) the timeout is
also important because we don't want to round up partial milliseconds if
the start time was sampled near the end of a millisecond boundary. The
timeouts of eeproms can be ~5ms.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
A call to atomic_set_bit_to() was used for clearing bits in an atomic_t
variable that stores information about allocated GPIOTE channels.
This caused an issue to be reported by Coverity, as the function treats
its first parameter as an array and it was provided with a pointer to
a singleton.
This commit replaces that call with atomic_and(), to prevent the issue
from being reported and for consistency with the way bits are set for
allocated GPIOTE channels (what is done with a call to atomic_or()).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The STOPTX task cannot be triggered directly in the function that
disables TX interrupt because this task stops the UART transmitter
immediately, even if it is in the middle of shifting out a byte.
Instead, this task needs to be triggered in the interrupt handler,
when the end of transmission is signaled.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
To keep the bus fully loaded, the SAM0 has a fast path that recognises
special cases like TX only, RX only, or TX/RX of the same size.
Commit #ea2431f32f7 accidentally disabled this.
This increases the utilisation from around 30 % to around 90 % at 48
MHz.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 has a data register and a shift register. Data that is
written to the data register is transferred to the shift register by
the peripheral.
On the SAMD51, the CPU is fast enough that the first data write hasn't
been transferred to the shift register by the time the next data write
occurs, causing the second write to be dropped, causing the receiver
to wait forever.
Fix by spinning until the data register is empty.
Signed-off-by: Michael Hope <mlhx@google.com>
The gd7965 driver still called ksleep with unsigned integers.
Use the K_MSEC makro instead.
Signed-off-by: Tobias Schaffner <tobiasschaffner87@outlook.com>
Adds the chip select devicetree flags to the spi_cs_control instance.
ISM43362 chip select is ACTIVE_LOW.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Fix host RX thread being deadlocked. The deadlock occurs because the
RX thread is stuck waiting in conn_tx_alloc with K_FOREVER but if the
connection is disconnected only the RX thread can unblock it in the
handling of the disconnect event.
This commit fixes this deadlock by splitting the processing of the
disconnected event into two parts.
The part needed to unblock the RX is to release resources held by
unack'ed TX packets and mark the connection state as not connected
anymore.
The RX thread waiting for free_tx fifo and the TX thread waiting for
the bt_dev.le.pkts semaphore will both check the connected state after
having acquired them and will abort if disconnected.
The rest of the processing will be handled at normal RX thread
priority like normal.
Move the bt_recv_prio handling to the Bluetooth host when the host
has defined its own RX thread (CONFIG_BT_RECV_IS_RX_THREAD=n).
If the HCI driver has the RX thread (CONFIG_BT_RECV_IS_RX_THREAD=y),
then the responsibility to call bt_recv and bt_recv_prio correctly
falls to the HCI driver.
The helper function bt_hci_evt_is_prio() is replaced with
bt_hci_evt_get_flags() so that the HCI driver can do this correctly.
This decision to replace was made so that existing HCI drivers
maintained out-of-tree will fail at compile time with the new system.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Bluetooth: host: Move bt_recv_prio to host when RX thread is defined
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
We should not set PLLSRC bits here. It is done by
LL_PLL_ConfigSystemClock_* functions which are called later.
Also, PREDIV1 setting should not be restricted to HSE only.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Add a Kconfig option for enabling the DAC test output. On the NXP
KE1xF the DAC test output is internally routed to ADCx SE23.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add support for STM32L0X using the generic STM32 backend. This is
quite a significant change since the L0 series uses a slightly
different flash controller. Refactor the generic backend to better
support different block sizes and the L0's register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Several STM32 chips have identical chip-specific code that has been
duplicated in different source files. Unify the F0x, F1x, and F3x to
use a single implementation.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
ringbuf claim API returns pointer to contiguous area. In cases when data
in ringbuf wraps the end of internal buffer, then single call to claim
data is not enough to get all data - there is remaining part on the
beginning of internal buffer. Those remaining bytes will need to wait
for next ISR handler to trigger workqueue. Theoretically this means that
data on the beginning of ringbuf can wait there forever, or simply to
the next timeout in PPP stack when data traffic continues.
Consume data from ringbuf in a loop, stopping only when claiming results
in empty buffer. This will make sure that there is no stale data in the
ringbuf.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Claimed ringbuf bytes were parsed until first frame was detected, but
remaining data in the claimed area was just ignored / lost.
Continue parsing bytes to the end of claimed area after each detected
frame.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
CLOCK_STM32_PLL_XTPRE Kconfig symbols was made to differentiate
code between F1 soc variants with XTRE and others.
It appears that specific XTRE code handling is already in place in
LL_PLL_ConfigSystemClock_* functions that are called afterwards.
Since this piece of code is not required anymore, let's remove
the symbol.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
- Fix passive mode protocol selection depending on AT versions
- Use Kconfig value for reset timeout
- Fix bug with parsing security from scan result
- Re-order some AT commands during init due to some commands having
dependency on other commands
Signed-off-by: Tobias Svehagen <tobias.svehagen@gmail.com>
Implemented rf2xx_set_txpower() in ieee802154_rf2xx.c by mapping dBm
values to RF2XX register values.
Signed-off-by: Kari Severinkangas <kari.severinkangas@tridonic.com>
Signed-off-by: Markus Becker <markus.becker@tridonic.com>
Remove K_FOREVER wait on completion_sync.
In some situations (a short on I2C SDA line for example), this
semaphore will never be released and therefore we should not wait
it forever.
Instead we wait for a maximum of 100msec and return an error if we
weren't able to retrieve the semaphore.
In such situation, the program is not stuck anymore, but the I2C
driver must be uninit then init again to work again.
Fixes#25076.
Signed-off-by: Xavier Chapron <xavier.chapron@stimio.fr>
The driver should only call net_pkt_unref on packets that get
successfully handled, ie where send/sendto return 0. If the packet
cannot be handled, net_context layer still owns the packet and should
take care or the unref.
Signed-off-by: Tobias Svehagen <tobias.svehagen@gmail.com>
The Atmel GMAC Ethernet driver may be used by both the SAM series
(e.g. SAM E70) and SAM0 series (e.g. SAM E54) SoCs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
When writing buffers larger then page-size, there is already a routine
that checks wrap around and adjusts offsets, but this routine was
missing incrementing the data pointer, which would results in
rewriting the same page-size bytes over and over. This adds the proper
increment code.
Signed-off-by: Fabio Utzig <fabio.utzig@nordicsemi.no>
Silence a gcc warning due to possible return of unitialized variable in
erase function. This could only happen if size == 0, which doesn't seem
likely, but initializing the variable to zero should fix the issue.
Signed-off-by: Fabio Utzig <fabio.utzig@nordicsemi.no>
Add support for the SX126x series of LoRa radios using the
LoRaMAC-Node HAL.
This driver currently makes the following assumptions:
* DIO1 is used as an interrupt line.
* There is an RF switch selecting between the TX and RX ports and
that switch is controlled by DIO2.
* There is either no TCXO or the TCXO is controlled by DIO3.
Specifically, the limitations above mean that modules that use GPIOs
to control the RF switch are currently not supported. Support for such
modules would need changes to the LoRaMAC-Node code.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Add a new configuration option, LORA_SX12XX, that is shared for all of
the LoRaMAC-node-based radio drivers. By default, the appropriate
driver for the LoRa radio in the device tree is included is included
in the build.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Some boards may include an APA102 LED on an existing SPI bus. With
additional circuitry, chip select is supported where the APA102
lacks a built in CS pin.
This patch allows CS to be defined in the devicetree (through .dts
files) and utilised in the apa102.c driver if it's available. Preserving
old behaviour if no chip select is defined.
Signed-off-by: Roman Vaughan <nzsmartie@gmail.com>
Adds optional device tree properties to set delays between spi chip
select assert/deassert and clock edges in the mcux dspi and lpspi
drivers. If these properties are not set, then the minimum supported
delays are used.
Verified that tests/drivers/spi/spi_loopback/ still passes on
mimxrt1050_evk (lpspi driver) and frdm_k64f (dspi driver).
Measured with a scope that the pcs-sck-delay and sck-pcs-delay times on
the first spi transaction in the test are reduced from 7.82 us to 20 ns
on mimxrt1050_evk.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add an additional option to the spi_cs_control struct that records how
the pin has been configured in devicetree. For drivers that are not
updated, the CS behaviour is the same as before (Push-Pull).
Use the devicetree knowledge with the GPIO subsystem so that the correct
physical pin levels for the CS pin are automatically selected.
Fixes#26267
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
PCIe shell was enabled by default if shell is enabled in below commit:
commit ee985d81aa ("shell: enable modules by default if shell is
enabled").
However, this shell file has tests for PCIe RC, not applicable to EP.
So, should not be default enabled for PCIe EP.
If we add EP shell tests in future, they should be added under
drivers/pcie/endpoint/ directory.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This runs the Timer/Counter for Control in 'normal' PWM mode. The
number of channels and counter width depends on the device and is
imported from DeviceTree.
Signed-off-by: Michael Hope <mlhx@google.com>
Add api to raise SGI to target cores in affinity level identified
by MPIDR. Currently only EL1S is supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
The front side bus interrupt delivery feature is a somewhat obscure
part of PC history (in some sense a presaging of MSI interrupts) that
we don't use.
But it's part of the spec, works on hardware, has precedence over the
"legacy" interrupt routing feature we do use, and can be legally
enabled by firmware.
Disable at init time.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a typo in the function pointer assigned to get_parameters. It
should be flash_sam_get_parameters.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occur.
A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.
GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.
GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.
Hence a dsb can ensure from core no writes are issued before the
previous writes are *complete*.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Right now we depend on NEWLIB_LIBC to build Zephyr with LORA=y. This
seems to be the only Kconfig option like that. Convert it to select
REQUIRES_FULL_LIBC instead, which will select NEWLIB_LIBC by default and
allow to use external libc as well.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
In sensors drivers, in gpio callback function :
The device structure in parameter is related to the gpio device.
Signed-off-by: laurence pasteau <laurence.pasteau@stimio.fr>
Commit id a538dcd8f8 got rid of the usage of these pointers so they are
useless now and can be removed in this drivers.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert the present initialization code into initialization macros.
Since both the uart and the usart peripheral is implemented, two sets
of initialization macros are necessary.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Parsed value is expected to be in range (0, UINT32_MAX). Use strtoul
instead of strtoll, so we better match its range. In a tested
configuration this saves 380 bytes of flash with newlib and arm32
target.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This enables the ACPI_EC1 interface which is typically accessed
through ports 0x6A0 and 0x6A4 in Bios.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
For some reason, use of the DT_NUM_INST macro in this driver was not
replaced with DT_NUM_INST_STATUS_OKAY. In consequence, this driver
could not be compiled successfully. Furthermore, because this now
undefined macro had been used inside UTIL_LISTIFY, gcc was not even
able to report an error, instead the compilation just "froze".
This patch replaces UTIL_LISTIFY(DT_NUM_INST()) with more appropriate
in this context DT_INST_FOREACH_STATUS_OKAY. It also adds an apparently
missing inclusion of sys/byteorder.h.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
pcie has an all in one command for listing pci devices. Make it support
additional commands and move lspcie to `pcie ls`.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If shell is enabled then enable all sub-shells if their dependencies are
satisfied. This was done for some modules and subsystems but was not
consistent.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Printing the file descriptor does not give any information when
the network interface creation fails, so print errno here instead.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
The driver was returning zero due to accessing the, say, 0x81'th
endpoint instead of the 0x01'th endpoint.
Signed-off-by: Michael Hope <mlhx@google.com>
Espi has three uart port from 0 to 2 and uart sirq need to enabled for
the port which is active in the hardware. An active uart sirq shoudl be
enabled based on uart mapping configuration.
Signed-off-by: Venkataramana Kotakonda <venkataramana.kotakonda@intel.com>
All pinmux supporting CAN, SPI and I2C of F7 series are added.
Since the F7 series supports up to two CANs,
the pin names of CANs have been changed.
Several minor pinmux errors have also been fixed.
Sorted by Alternate function.
Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
Avoid reading LPTIM counter four times instead of three when second
read doesn't give same value. Use common code, avoid volatile for
local vars.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
According to RM, when increasing the CPU frequency, the new number of
wait states to the Flash latency bits must be written and verified
before modifying the CPU clock source and/or the CPU clock prescaler,
to prevent NMI to occur; when decreasing the CPU frequency, after.
Tested with STM32L462 SOC and MSI with several frequencies, both
increasing and decreasing. HSE built, not tested.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi@nexxiot.com>
Several shell modules use cloned code to iterate over all devices and
identify the nth instance that meets some criteria. The code was
repetitive and included various errors. Abstract to a helper function
that performs the check consistently.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
RF SPDT switches used for RX/TX selection have often power enable pin
connected to MCU's GPIO, so it is possible to disable it to save power
when not doing any data transfers. Add 'antenna-enable-gpios' property
to support such designs.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Add support for TCXO power control using GPIO pin. Some boards
(including B-L072Z-LRWAN1 already supported in Zephyr) need delay
applied after powering on TCXO, so add device-tree property allowing to
configure that as well. Cache information about TCXO power status, so
subsequent requests to enable it will not result in unnecessary delays.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
There are several antenna path designs on SX1276 compatible boards in
the wild. B-L072Z-LRWAN1 board has dedicated enable pins for RFI, RFO
and PA_BOOST. This is exactly what this patch allows to
configure. Second variant of antenna selection is done with a single
GPIO pin, which controls RF SPDT switches (input or output). This is
also supported, when either 'rfo-enable-gpios' or
'pa-boost-enable-gpios' property is provided alone (RFO/PA_BOOST is
selected only when transmitting, so there is no need for explicit
'rfi-enable-gpios' configuration).
Drop requirement for 'power-amplifier-output' DT property when there is
either 'rfo-enable-gpios' or 'pa-boost-enable-gpios' configured. Fail
using BUILD_ASSERT() when neither is specified.
Make the SX1276SetAntSw() logic similar to loramac-node examples
implementation, so RFO/PA_BOOST is enabled only in
RFLR_OPMODE_TRANSMITTER.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
PA selection mainly depends on board design. So it looks like
device-tree is a better mechanism than Kconfig in this case. Use string
property with two possible values: "rfo" and "pa-boost".
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
All fields in PA_CONFIG register are set explicitly, so there is no need
to read this register first.
Suggested-by: Andreas Sandberg <andreas@sandberg.pp.se>
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
The PA_CONFIG register is currently not setup correctly for the RFO
path. The biggest problem is that the output power is incorrectly set
1dBm higher than requested. Additionally, the lower power levels are
not configured properly since the max power field in PA_CONFIG is
always configured for an output power between 0 and 15dBm.
To support lower than 0dBm, adjust the max power field in the
PA_CONFIG register to shift the output power range to -4--11 dBm when
the requested power is 0 or lower.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[Marcin: rebase on master]
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Some flash controllers support operations only when buffers are word
aligned. An example of such is nRF QSPI, which checks input buffer using
nrfx_is_word_aligned() function inside nrfx_qspi_write().
Align test array on 4 bytes, so we will gain compatibility with more
flash controllers, including nRF QSPI.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
With addition of flash_parameters structure, and supporting API call
to retrieve it, it is no longer needed to store write_block_size as
a part of flash_driver_api and it should be part of flash_parameters.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
With addition of flash_get_parameters API call, it is needed to provide
support for the API to flash drivers.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Add support to register callback function for each PCIe reset.
These callback functions are executed from corresponding
PCIe reset interrupt handler if registered.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add reset interrupt handlers for all three types of reset
interrupts that iProc PCIe EP can receive - namely PERST,
INB PERST and FLR.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add support for the polarity flag in the STM32 PWM driver.
STM32 boards using PWM have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The PWM drivers has been refactored using the HAL LL API. Not only that,
but the set pin_set function is now faster, as channel output compare is
just initialized if needed.
NOTE: Has been tested using H743zi board for now.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a DSB before doing WFE in get_entropy_isr, to ensure
the memory transactions are complete.
Add a note clarifying a dependency for the existing solution
(dependency is satisfied by ARCH code but is good to state
clearly).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We need to clear the NVIC Pending bit for the RNG IRQ before
doing any WFEs and expect to wake up by RNG events. This is
because the event register will be set only if NVIC status
is changed from 0 to 1.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Appropriate WS can be loaded automatically if
the display controller has integrated temperature
sensor or an external sensor is connected.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Fixes the bq274xx sensor driver to check the i2c device pointer is
non-null, rather than the bq274xx sensor device pointer. This appears to
be the originally intended check based on the LOG_ERR message.
Coverity CID: 210035
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Initialize the dummy data transfer so spi transfer is defined even for
an undefined tx data buffer. This aligns the rv32m1 spi driver with the
mcux spi driver.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Aligns MAC registers to the latest reference manual.
Replaces NULL buffers as some SPI drivers will fail.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The CONFIG_BT_RPMSG_NRF53 should depend on the SOC, not the BOARD
definition. Otherwise this will break for custom boards.
Signed-off-by: Thomas Stenersen <thomas.stenersen@nordicsemi.no>
This commit removes API functions and macros which were deprecated in
2.2 release. GPIO drivers are updated accordingly.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Modified order of reported events on rx disable to match API
description: first RX_RDY and then RX_BUF_RELEASED.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
So far, when rx_disable was called then received data was discarded.
This is currently not according to the API but it is needed if
rx_disabled is called due to out of band information about end of
packet.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
So far, when rx_disable was called then received data was discarded.
This is currently not according to the API but it is needed if
rx_disabled is called due to out of band information about end of
packet.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The HPET timer was hard-coded to support only edge triggering
interrupts. This adds the necessary bits to enable level
triggering for the timer.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
DMA driver shall be initialized before any of its
clients. Right now, its initialization priority is
lower than that of UARTs. So, increase its init
priority to support future async uart drivers.
Signed-off-by: Jun Li <jun.r.li@intel.com>
- Change default CPU Clock to 240MHz
(PLL is activated)
- I2C, UART will use sysclk from clock driver
- esp32_enable_peripheral replaced by
clock_control_on
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
Allow passing the channel as a number instead of a string in order to
support sensor-specific channels (channel SENSOR_CHAN_PRIV_START and
up).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Enable VLAN support so that this driver can be used to test
the VLAN when using qemu_x86 board.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This change removes references to raw POSIX types and functions,
allowing the drivers to build without NET_SOCKETS_POSIX_NAMES.
After this, the dependency between NET_SOCKETS_OFFLOAD and
NET_SOCKETS_POSIX_NAMES can be removed.
See issue #26033 for additional context
Signed-off-by: Adam Porter <porter.adam@gmail.com>
The driver currently blindly copies all of the outgoing bytes into the
endpoint. Instead, calculate the endpoint size and copy up to that
amount instead.
Signed-off-by: Michael Hope <mlhx@google.com>
A non-blocking, isr-safe version of get_entropy() is necessary in order
to be called during boot time before POST_KERNEL initialization.
Otherwise a crash is seen as the existing get_entropy() implementation
uses k_sem and relies on interrupts.
Fixes#18629
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
