This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.
STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...
The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.
Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Make driver generic for multiple ILI displays. The adopted strategy is
to share all driver code except register initialization, which has been
found to have some specific registers/values depending on the
controller.
The driver has been adjusted to support multiple compatibles.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Introduce <dt-bindings/dt-util.h> file. It wraps <sys/util_macro.h>
file exposing all macro base definitions to DTS preprocessor. Once it
contains only prepocessor macros, it can be safely included in DTS,
similar way the <dts/arm/<manufacturer>/pinctrl_<manufacturer>_<soc>.h
files are included.
This provides necessary background to elaborate complex constructions
like variable length macros with zero or more elements.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
In npcx7 series, all of them support the Intel Enhanced Serial
Peripheral Interface (eSPI) Revision 1.0. This specification provides a
path for migrating host sub-devices via LPC to a lower pin count, higher
bandwidth bus. In addition to Host communication via the peripheral
channel, it provides virtual wires support, out-of-band communication,
and device mastering option over the Chipset SPI flash.
Becisdes introducing eSPI device in npcx7, this CL also includes:
1. Add eSPI device tree declarations.
2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI
Virtual-Wire signals, eSPI registers, and wake-up input sources.
3. Zephyr eSPI api implementation.
4, Add OOB (Out of Band tunneled SMBus) support.
5. Add configuration files for eSPI test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
On stm32f1 series, in output mode, there is no way to enable
pull-up/down resistors.
Clean these settings from helper defines.
Additionally add helper define to shorten few lines.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Macro STM32_PINMUX and related definitions are not compatible with
stm32f1 series and then should not be provided in -common.h.
Move them to stm32-pinctrl.h
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move pixel format setting (RGB565/RGB888) to DeviceTree. Add support for
changing pixel format at runtime.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds imx rt support.
Allows n-number of can interfaces based on device-tree.
Adds a "common" irq name.
Added CAN bus pins and dts for 1060 and 1064 EVK.
Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
The led-controller DT binding gathers some common properties for LED
controllers and for the LED child nodes.
One notable property is "color-mapping" which allows to define a channel
to color mapping for multicolor LEDs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Add clock controller support for Nuvoton NPCX series. This CL includes:
1. Add clock controller device tree declarations.
2. Introduce clock-cells in yaml file clock tree to get module's source
clock and turn off/on the its clock
3. Clock controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit adds a bindings for the clock controller used in lpc11u6x
MCUs. It also adds a clock-controller node for the lpc11u6x soc series.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
This patch adds the DT nodes and binding for the pinmux registers,
aka IOCON (I/O control), found on the LPC11U6x MCUs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Add device tree bindings for the Semtech SX1261 and SX1262
radios. These will be used by Zephyr's LoRa drivers.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Use '0xa0' as default priority to be consistent with the V1/V2 and
V3 drivers default priority init.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
This commit removes API functions and macros which were deprecated in
2.2 release. GPIO drivers are updated accordingly.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
This defines the configuration for the DMA client
as specifed in the ./dts/bindings/dma/st,stm32-dma.yaml
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When configuring the I2S peripheral as a master, the DMA channel
direction must be configured to transfer data from memory to the
peripheral.
Currently the configuration of channel direction is always set for
peripheral to memory regardless of whether it is the TX or the RX
channel.
Signed-off-by: Abe Kohandel <abe@electronshepherds.com>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
GPIO_DIR_OUT is deprecated but allowed in devicetree bindings because
some in-tree bindings provided it in the past. GPIO_DIR_IN was the
former explicit way of representing the default direction. Put it
back so symmetry is maintained.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Extend the physical level GPIO_OUTPUT_{HIGH,LOW} configuration with
GPIO_OUTPUT_{ACTIVE,INACTIVE} for logic level initialization.
This enables use of device-tree configuration flags in calls to
gpio_pin_configure() to set the logic level without having to
determine the corresponding physical level.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
gpio_pin_interrupt_configure() is invoked from within
gpio_pin_configure() to support legacy code that combines pin and
interrupt configuration. Expressing a disabled interrupt by a zero
value for interrupt flags causes this invocation to disable interrupts
when the intent is to change only a pin configuration, such as pull
direction.
Support a distinction between explicitly disabling interrupts and
leaving the interrupt configuration unchanged.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit makes following changes to GPIO dt-bindings flags:
- Added GPIO_ACTIVE_LOW, GPIO_ACTIVE_HIGH to indicate pin active state.
- Added GPIO_OPEN_DRAIN, GPIO_OPEN_SOURCE to configure single ended pin
driving mode.
- Added GPIO_PULL_UP, GPIO_PULL_DOWN flags.
- GPIO_INPUT, GPIO_OUTPUT to configure pin as input or output.
- Added GPIO_OUTPUT_LOW, GPIO_OUTPUT_HIGH flags to initialize output
in low or high state.
- reworked GPIO_INT_* flags to configure pin interrupts.
- following flags were deprecated: GPIO_DIR_*, GPIO_DS_DISCONNECT_*,
GPIO_PUD_*, GPIO_INT_ACTIVE_*, GPIO_INT_DOUBLE_EDGE, GPIO_POL_*.
To be aligned with Linux DTS standard any GPIO flags that should not be
used in DTS files are moved from include/dt-bindings/gpio/gpio.h file to
include/drivers/gpio.h with an exception of several old flags which
removal would cause DTS compilation errors. Those remaining old flags
will be removed from include/dt-bindings/gpio/gpio.h at a later stage.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This patch introduces the periph to/from memory dma transfer
define new values for dma cells on client side
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for requesting an inverted PWM pulse (active-low) when
setting up the period and pulse width of a PWM pin. This is useful
when driving external, active-low circuitry (e.g. an LED) with a PWM
signal.
All in-tree PWM drivers is updated to match the new API signature, but
no driver support for inverted PWM signals is added yet.
All in-tree PWM consumers are updated to pass a flags value of 0
(0 meaning default, which is normal PWM polarity).
Fixes#21384.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.
This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.
SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].
This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.
The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move the selection of the IP clock source for the modules in the NXP
Kinetis KE1xF SoCs from being hardcoded in soc.c to being specified in
the device tree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove the handcoded multi-level IRQ values in device tree. We now are
able to generate the encoded multi-level IRQ value.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To work efficiently, SPI_NSS pins require pull-up configuration.
Fix this for whole STM32 series.
Fixes#17998
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The GIC400 is a common interrupt controller that can be used with the
Cortex A and R series processors. This patch adds basic interrupt
handling for the GIC, but does not handle multiple routing or
priorities.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Add enum to list what values of maximum-speed are exceptable since
enum's get represented as strings in DT. This also allows us to
generate a code enum to correspond to the string.
We also introduce include/dt-bindings/usb/usb.h which is a hand coded
definition of the enum. We don't have a great way to generate this
right now, however it would be better if we did.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If a UART is configured with IRQ == PCIE_IRQ_DETECT, then use the
pcie_wired_irq() to determine the IRQ at runtime, and install the
handler using the dynamic interrupt mechanism.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
