Add support for the polarity flag in the STM32 PWM driver.
STM32 boards using PWM have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The PWM drivers has been refactored using the HAL LL API. Not only that,
but the set pin_set function is now faster, as channel output compare is
just initialized if needed.
NOTE: Has been tested using H743zi board for now.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a DSB before doing WFE in get_entropy_isr, to ensure
the memory transactions are complete.
Add a note clarifying a dependency for the existing solution
(dependency is satisfied by ARCH code but is good to state
clearly).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We need to clear the NVIC Pending bit for the RNG IRQ before
doing any WFEs and expect to wake up by RNG events. This is
because the event register will be set only if NVIC status
is changed from 0 to 1.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Appropriate WS can be loaded automatically if
the display controller has integrated temperature
sensor or an external sensor is connected.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Fixes the bq274xx sensor driver to check the i2c device pointer is
non-null, rather than the bq274xx sensor device pointer. This appears to
be the originally intended check based on the LOG_ERR message.
Coverity CID: 210035
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Initialize the dummy data transfer so spi transfer is defined even for
an undefined tx data buffer. This aligns the rv32m1 spi driver with the
mcux spi driver.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Aligns MAC registers to the latest reference manual.
Replaces NULL buffers as some SPI drivers will fail.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The CONFIG_BT_RPMSG_NRF53 should depend on the SOC, not the BOARD
definition. Otherwise this will break for custom boards.
Signed-off-by: Thomas Stenersen <thomas.stenersen@nordicsemi.no>
This commit removes API functions and macros which were deprecated in
2.2 release. GPIO drivers are updated accordingly.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Modified order of reported events on rx disable to match API
description: first RX_RDY and then RX_BUF_RELEASED.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
So far, when rx_disable was called then received data was discarded.
This is currently not according to the API but it is needed if
rx_disabled is called due to out of band information about end of
packet.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
So far, when rx_disable was called then received data was discarded.
This is currently not according to the API but it is needed if
rx_disabled is called due to out of band information about end of
packet.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The HPET timer was hard-coded to support only edge triggering
interrupts. This adds the necessary bits to enable level
triggering for the timer.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
DMA driver shall be initialized before any of its
clients. Right now, its initialization priority is
lower than that of UARTs. So, increase its init
priority to support future async uart drivers.
Signed-off-by: Jun Li <jun.r.li@intel.com>
- Change default CPU Clock to 240MHz
(PLL is activated)
- I2C, UART will use sysclk from clock driver
- esp32_enable_peripheral replaced by
clock_control_on
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
Allow passing the channel as a number instead of a string in order to
support sensor-specific channels (channel SENSOR_CHAN_PRIV_START and
up).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Enable VLAN support so that this driver can be used to test
the VLAN when using qemu_x86 board.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This change removes references to raw POSIX types and functions,
allowing the drivers to build without NET_SOCKETS_POSIX_NAMES.
After this, the dependency between NET_SOCKETS_OFFLOAD and
NET_SOCKETS_POSIX_NAMES can be removed.
See issue #26033 for additional context
Signed-off-by: Adam Porter <porter.adam@gmail.com>
The driver currently blindly copies all of the outgoing bytes into the
endpoint. Instead, calculate the endpoint size and copy up to that
amount instead.
Signed-off-by: Michael Hope <mlhx@google.com>
A non-blocking, isr-safe version of get_entropy() is necessary in order
to be called during boot time before POST_KERNEL initialization.
Otherwise a crash is seen as the existing get_entropy() implementation
uses k_sem and relies on interrupts.
Fixes#18629
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
iProc PCIe EP IP is present in Broadcom PCIe offload chips.
Add iProc PCIe EP driver to provide basic PCIe EP functionality.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Introduce common API to achieve data transfer using memcpy
to/from outbound region of PCIe EP.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add public APIs for PCIe endpoint driver:
- EP configuration space read/write
- Mapping/Unmapping of Host buffer and PCIe outbound region
- Raise interrupt to Host
These are minimal base APIs to make PCIe EP functional.
Also, add a Kconfig and an empty CMakeLists.txt for drivers to extend.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
The Nordic QSPI peripheral uses DMA transfers so data to write must be
located in SRAM. Add a Kconfig that enables copying data from NVMC to
a stack SRAM buffer so it can be written to flash.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
mcumgr and possibly mcuboot write single byte values to update the
state of objects. Rather than fail to do the write of values too
short for this peripheral detect the situation and write from a stack
buffer that meets the length criteria.
Signed-off-by: Sigvart Hovland <sigvart.m@gmail.com>
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Currently user is forced to configure an array of 4 IO pins. This makes
no sense when there are only 2 IO pins connected on board.
Configure 3rd and 4th pin in internal structure as
NRF_QSPI_PIN_NOT_CONNECTED if only 2 were specified in device-tree.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
The cs-gpios pin on SPI controller is optional for SPI controllers that
can automatically control CS line.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Extends the fix in commit 2175675199 to
all other mcux serial drivers. They were incorrectly checking if the
transmit buffer was empty when they should have been checking if the
transmission is complete.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The STM32L072CZ MCU has a built-in USB device controller which is
supported by Zephyr's USB STM32 driver. The b_l072z_lrwan1 board has a
micro-USB connector that is wired to the MCU via two solder bridges
(SB15 and SB16) that need to be closed to connect the data lines.
Update the board documentation to describe the solder bridges and
enable the USB controller in the device tree.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
