Convert older DT_INST_ macro use in arm_cmsdk/arm drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a fixed clock to the qemu-virt-a53.dtsi to match how the musca dts
files work so we get the clock DT info in the same way in the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In the DT_INST conversion we introduced a typo bug of accessing port0
instead of port1 in the IRQ config function.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The PrimeCell UART (PL011) IP can use one single combined/shared
interrupt line instead than different IRQ lines for TX/RX/Err/... This
is the most common configuration supported in the Linux world but not
currently supported in Zephyr. QEMU emulates a PL011 UART with a single
interrupt line as well.
To support this configuration we have to hookup the PL011 driver with a
shared IRQ driver and add two new configuration options when the shared
IRQ line is used.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The driver fails to compile when CONFIG_UART_INTERRUPT_DRIVEN=n. This is
due to a nested ifdef on CONFIG_UART_INTERRUPT_DRIVEN that is excluding
pieces of code unrelated to the uart interrupts management.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The PL011 driver is not specific to the cortex_m arch and the driver
does not really use anything from the cmsis header file. Remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The uart_pl011 driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
move uart.h to drivers/uart.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch changes the ICR masking to use a fixed mask instead of
a buggy read/write of the current ICR to itself. The ICR is write
only and reading this for information is unpredictable and should
be avoided.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds a serial driver for the ARM PL011 IP block.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
