As I2C_0 (port 0) isn't used on the STM32 platforms we didn't exclude
the related Kconfig options if DTS was enabled. However other SoCs
(like NXP) do use I2C_0 so we need to fixup the Kconfig dependencies
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
patch uses chosen property zephyr,bt-uart, zephyr,uart-pipe
and zephyr,bt-mon-uart to determine the uart instance to be
used for bluetooth,uart_pipe and bluetooth_monitor and generate
appropriate configs.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
It is incorrect to call spi_context_release() on a
spi_dw_data object's ctx field before data->ctx->config is first
set in spi_dw_configure(). This is because spi_context_release()
reads ctx->config->operation. In particular, during spi_dw_init(),
calling spi_context_release() reads the uninitialized memory in
spi->ctx->config->operation.
Call spi_context_unlock_unconditionally() instead to properly increase
the semaphore count.
Without this patch, the first call to spi_transceive() can block
forever depending on the value of the uninitialized memory holding
spi->ctx->config->operation.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
It is incorrect to call spi_context_release() on an STM32
spi_stm32_data object's ctx field before data->ctx->config is first
set in spi_stm32_configure(). This is because spi_context_release()
reads ctx->config->operation. In particular, during spi_stm32_init(),
calling spi_context_release() reads the uninitialized memory in
data->ctx->config->operation.
Call spi_context_unlock_unconditionally() instead to properly increase
the semaphore count.
Without this patch, the first call to spi_transceive() can block
forever depending on the value of the uninitialized memory holding
data->ctx->config->operation.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Added BUILD_ASSERT check for Tx and Rx thread priorities.
The Tx thread priority shall be higher than Rx thread
priority in order to correctly detect transaction violations
in ATT and SMP protocols. The Number of Completed Packets
for a connection shall be processed before any new data is
received and processed for that connection.
The Controller's priority receive thread priority shall be
higher than the Host's Tx and the Controller's Rx thread
priority.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Until Zephyr has infrastructure to enable/disable the
reception of multicast frames we disable the hardware
multicast frame filter completly and pass all multicast
frames to the upper layer and let that deal with them.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
We can use the chosen property "zephyr,console" to determine what uart
should be used as the console and find its name to generate a define for
CONFIG_UART_CONSOLE_ON_DEV_NAME.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Frequency tolerance for LFRC after calibration for nRF5x
Series ICs is between 251 and 500 ppm as per Product
Specification. For more details refer to:
http://infocenter.nordicsemi.com/
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
By the time we get to POST_KERNEL, kernel services and kernel objects
should be available for use. This should include timers and the random
number generator, but we don't init the system clock until sometime
during the POST_KERNEL phase. Initialize it earlier.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Upcoming memory protection features will be placing some additional
constraints on kernel objects:
- They need to reside in memory owned by the kernel and not the
application
- Certain kernel object validation schemes will require some run-time
initialization of all kernel objects before they can be used.
Per Ben these initializer macros were never intended to be public. It is
not forbidden to use them, but doing so requires care: the memory being
initialized must reside in kernel space, and extra runtime
initialization steps may need to be peformed before they are fully
usable as kernel objects. In particular, kernel subsystems or drivers
whose objects are already in kernel memory may still need to use these
macros if they define kernel objects as members of a larger data
structure.
It is intended that application developers instead use the
K_<object>_DEFINE macros, which will automatically put the object in the
right memory and add them to a section which can be iterated over at
boot to complete initiailization.
There was no K_WORK_DEFINE() macro for creating struct k_work objects,
this is now added.
k_poll_event and k_poll_signal are intended to be instatiated from
application memory and have not been changed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The controller and host-side RX threads recently had their priorities
lowered to 8. Make the driver RX threads consistent with this.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Configure I2C using DT for the following STM32 boards:
disco_l475_iot1
nucleo_f401re
96b_carbon
olimexino_stm32
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The SAM4S, SAM3X, SAME70 all use the uart_sam.c serial
driver. This patch puts the configuration in DTS and
out of Kconfig. The SAME70 uses the USART as well.
USART DTS support for the SAME70 is also in this patch.
Signed-off-by: Justin Watson <jwatson5@gmail.com>
The I2C Slave Read support isn't well defined and not actually supported
by any i2c driver at this point. We can add this back when slave mode
is more thought out.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a STM32 LL based driver for the RNG processor. The RNG processor
is a random number generator, based on a continuous analog noise, that
provides a random 32-bit value to the host when read. The RNG passed
the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Add support for KW40Z in the KW41Z IEEE 802.15.4 driver as both chips
expose almost the same radio registers.
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
The chip seems to require a wait time before reading packet
data after the RX sequence done interrupt, as imidiate reading
of it will indicate a packet size of zero and cause the RX
sequence done to be continually retriggered.
In addition, the extra clearing of the interrupt flags can be
removed, as this is already done at the beginning of the isr.
Jira: ZEP-2278
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
When building tests/kernel/test_build/test_debug on disco_l475_iot1 we
get the following build error:
drivers/i2c/i2c_ll_stm32_v2.c: In function ‘stm32_i2c_configure_timing’:
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4xx.h:207:38: error: ‘timing’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
^
drivers/i2c/i2c_ll_stm32_v2.c:265:8: note: ‘timing’ was declared here
u32_t timing;
^~~~~~
Fix by initializing timing to 0.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Following implementation of LL based SPI driver,
add SPI support on nucleo_f334r8 board of STM32F3 series.
Change-Id: Ifbe39b1f2cecdd7db23be9c6943a914a155ebd77
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add SPI pin for the nucleo_f401re pinmux.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add a SPI master and slave driver for the L4, F4 and F3 STM32
SoCs families.
Change-Id: I1faf5c97f992c91eba852fd126e7d3b83158993d
Origin: Original
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Tested-by: Lee Jones <lee.jones@linaro.org>
As not all drivers support interrupts we don't have a means to know if
we can allow UART_INTERRUPT_DRIVEN to be enabled and thus various
Kconfig options that select UART_INTERRUPT_DRIVEN. Some drivers have a
interrupts, however not all do. So introduce a Kconfig option to let us
know what the driver actually supports.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In added mode flash operation are performed in timeslice
(in radio idle time).
Kconfig for mode enabling CONFIG_SOC_FLASH_NRF5_RADIO_SYNC.
Erase and write API implementations were rewritten and preserved against
concurrent execution.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add configuration, documentation, pinmux, fixup and dts support for
STM32F103x8 based Minimum System Development board.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
as config SPI_CS_GPIO was selecting GPIO instead it
should just depend on it. This patch is a fix for
ZEP-2071 jira.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
patch enables qmsi serial driver to pick baudrate and name
from device tree instead of Kconfig for UART0 and UART1
instance
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
The esp-idf package contains on the BSP a definition of the BIT macro
unconditionally #defined when rom/uart.h is #included. When Zephyr's
uart.h (which pulls in include/misc/util.h) that conditionally
This generates a compile warning on the re-definiton of BIT by the
esp-idf package.
Thus include uart.h after esp-idf's rom/uart.h to have BIT not
re-defined thanks to Zephyr's conditional definition.
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
This is a minimal driver enabling console output during the port
bringup. While the driver works, only one of the three UART devices
are supported, and there isn't any way to change any parameters or
use interrupts. This will most likely be superceded by a proper
driver after the port has matured.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Update driver to use DTS-generated #defines for port names,
and not obsolete Kconfig variables.
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
L4 write access requires 64 bits alignment
while L4 read access does not require any alignment.
To support specific check according to read/write,erase
a parameter is added to stm32_valid_range.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
L4 have 64 bits write access.
The cast to 64 bits data address in write_dword
requires 3 right shifts on i (byte index) else the
data taken are wrong for i different from 0
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
We always have UART_IRQ_FLAGS set to 0, so just call IRQ_CONNECT with a
0 argument for the flags, and remove the UART_IRQ_FLAGS. This is
towards support for using the driver on the TI CC2650. (we add a
comment about that as well).
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit fixes the compilation error that occurs if both UART
ports on the FE310 SoC are enabled. The error occurs due to the
missing function definition of uart_fe310_irq_cfg_func_1 .
Signed-off-by: Jens Peter Schroer <jens@manetos.com>
Refactor internals of IPM driver removing bitfields and byte access of
32 bit registers.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The current method of accessing 32-bit data and control registers does
not work for all quark architectures. Sometimes writing to those
registers byte-by-byte results in last byte occupying whole 32 bit
register.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add necessary board files, pinmux and device tree in order to have a
usable debug console.
Origin: Original
Change-Id: I43a9d278c3f2c936a714263626722f630367b663
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Following migration of stm32f1xx series clock control driver to
STM32Cube LL API, cleanup stm32 code base in order to take into
account that this is the only clock driver available for stm32
family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following introduction of stm32cube LL based clock control driver,
remove references to former native driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before introduction of LL based clock control for stm32f1xx series,
prepare gpio driver to provide useful definition for new API
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Align stm32f1xx series clock driver to other parts of stm32 family.
Driver support both Connectivity and Density lines of stm32f1 series,
that are based on different Reset and Clock Control architectures.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The Nucleo STM32F413 board is missing the default pinmux for PWM2 on
PA0, as stated in the doc. The same pinmux is also done for other
similar Nucleo board. So add it!
Change-Id: I2086c0a4ce65d68455a0978570f118e965f4c6ca
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Atmel SAM3X series has been recently converted to use ASF
and should now use common SAM family drivers. The atmel_sam3
serial driver will be removed in the future.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Fix nRF RTC timer from returning more than actual cycles
in _timer_cycle_get_32, under race condition when ISR
announces to kernel.
Jira: ZEP-2229
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Instead of NULL terminated buffer arrays, let's add a parameter for each
that tells the number of spi_buf in it.
It adds a little bit more complexity in driver's side (spi_context.h)
but not on user side (bufer one has to take care of providing the NULL
pointer at the end of the array, now he requires to give the count).
This will saves a significant amount of bytes in more complex setup than
the current dumb spi driver sample.
Fix and Use size_t everywhere (spi_context.h was using u32_t).
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The code was so far requesting 5 ms refresh timer, however with a
default TICKS_PER_SECOND=100 this was always rounded up to 10 ms,
causing some flickering. The closest TICKS_PER_SECOND that will give
flicker-less display but also give optimal ms-to-ticks calculations is
250, so change the timer to match that. After this change any code
using the display is recommended to set 250 as ticks per second.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
atmel_sam watchdog driver was temporarily limited to SAME70
series only. Now that all SAM series are using ASF the
change can be reverted.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Until we have better solution, we enable promiscuous mode as a
workaround to get IPv6 neighbour discovery going. Kconfig had
typos/thinkos preventing that to work however.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Source had CONFIG_ETH_MCUX_PHY_DETAILED_DEBUG, while Kconfig had
CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG. Use the shorter name consistently.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Documentation doesn't specify if this function may return 0, so add an
inexpensive check to account for this.
Jira: ZEP-2135
CID: 160954
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
If CS is controlled over GPIO, it will be possible to keep the slave up
and running (though no transaction will be going on) using this
configuration bit.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
SPI_HOLD_ON_CS can be used to ask the SPI device to keep CS on, after
the transaction. And this undefinitely, until another config is used.
This will inhibate the gpio cs delay, if any. This might be useful when
doing consecutive calls on one slave without releasing the CS.
SPI_LOCK_ON is to be used with caution as it will keep the SPI device
locked for the current config being used after each transaction. This
can be necessary if one needs to do consecutive calls on a slave without
any olher caller to interfere.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
All is done through the generic spi_context driver's API as it will be
generic to all SPI drivers.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Adding a struct k_poll_signal parameter to driver's API unique
exposed function.
If not NULL, the call will be handled as asynchronous and will
return right after the transaction has started, on the contrary
of current logic where is waits for the transaction to finish
(= synchronous).
In order to save stack, let's move the device pointer to struct
spi_config. So the call is still at a maximum of 4 parameters.
Adapting spi_dw.c and spi driver sample to the change so it still
builts.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
All SPI drivers have this same way to handle synchronous call, thus
let's generalize it in struct spi_context, with a relevant API and apply
the change into SPI DW driver.
spi_context API will prove to be useful once asynchronous call will be
handled as well, through the same completion functions used now only for
synchronous call. It will be transparent for the driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Let's improve common SPI driver context by adding a lock and generic
function to get/release it.
It's statically initialized to save a bit of ROM.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Introducing as well a generic driver helper for CS gpio control and
buffer management.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Such API improves many aspects of the former API by reducing the number
of function, allowing more buffer flexibility etc... This leads in
better memory usag and performance as well.
However, as this will take sometime to get into use, the former API is
still present and is the one enabled by default.
Jira: ZEP-852
Jira: ZEP-287
Jira: ZEP-1725
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
One liners if/for/while statements still need {}
(and line break are cheap for clarity).
Aligning parameters properly.
Also, removing __func__ usage from SYS_LOG_* as these macros already put
it internally.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Removed the old PWM APIs usage and added support for the new PWM API.
JIRA: ZEP-2018
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The data fragments were stored in reversed order when the RX
data was saved into network buffers. This was caused by net_pkt
changes in commit db11fcd "net/net_pkt: Fully separate struct
net_pkt from struct net_buf".
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
The STM32L4x SoCs embeds a slightly different embedded flash controller
from the STM32F4x SoCs.
This particular controller has the following properties :
- Up to 2 512KiB banks divided in 2KiB pages
- Flash can be accessed in any sizes
- Flash must be written in 64bit aligned 64bit double-words
The drivers/flash/flash_stm32f4x.c is refactored into a new common
drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is
created with the STM32L4x specific functions.
To ease the refactoring and keep common functions, the STM32L4x flash
headers are slightly modified to match the hardware reference naming
and solve compilation issues.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
