Check clock_control_on return value now that it is checking appropriate
bus is used in the request.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
CONFIG_CLOCK_STM32_APB2_PRESCALER does not exist for STM32F0 as it was
removed from the RCC Kconfig by commit d0678201c3 ("drivers:
clock_control: provide support for stm32f0."). This will break the PWM
driver if compiled for STM32F0.
Conditionally disable usage of this symbol for STM32F0 as all PWMs are
on APB1 for this family.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
PWM1 / PWM15 / PWM16 and PWM17 on STM32F0 do not use the same clocks
compared to the other series.
Add the STM32F0-specific clocks where needed.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
Not all PWM clocks belong to the GRP1, for example TIM1 on STM32F0. Add
the group information to the macro to enable supporting these PWMs in
the future.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
The prescalers are currently hardcoded and are not user-selectable. As a
result, the frequency of the timer can be inadequate to the task. For
instance, the frequency of the 16-bit timers (prescaler 10000) is
usually too low to correctly generate of PWM of a few kilohertz.
Hardcoded prescalers are replaced by Kconfigs so the user can choose at
compile time. The default value of each Kconfig matches the hardcoded
prescaler, so the change will be transparent.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
All the PWM between 1 and 20 can be found on the STM32 depending on the
serie and the specific model. Add all the missing PWMs up to PWM20 to
plan for the future needs.
Tested on STM32L496 with available PWMs.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
The registration of each PWM differs only by a few details.
These differences can be factorized in order to create a generic
registration macro.
This has several advantages:
- Less code
- Easier to add new PWM
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
TimerHandle->Init.Period is used to initialize TIMx ARR register. The
timer will count from 0 up to ARR including, thus it will tick
(ARR + 1) timers per period. As the "period_cycles" variable holds the
number of desired ticks, the ARR register is computed as
ARR = period_cycles - 1
Update the code to reflect this relationship. Otherwise the timer will
count one more tick for each period, leading to a wrong PWM frequency.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
When we called DEVICE_AND_API_INIT for PMW3, we accidently had
pwm_stm32_2 instead of pwm_stm32_3.
Fixes: #6625
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
RCC_HCLK_DIV1 translates to 0x0 while apb_psc uses the value defined
by CONFIG_CLOCK_STM32_APB1/2_PRESCALER (range from 1 to 16).
Manually check if the defined prescaler is 1 or not and use that to
calculate the correct timer clock.
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Add support for TIM3 as it is widely available and pins available via
headers on several devices.
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Following migration of stm32f1xx series clock control driver to
STM32Cube LL API, cleanup stm32 code base in order to take into
account that this is the only clock driver available for stm32
family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.
Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
After activation of cube based driver support on L4 and F3 series,
this commits performs the clean up of F3 and L4 relative code to
native clock control drivers.
Indirectly, it makes pwm driver supported de facto on F3 series
Change-Id: Idac17103a9b5ef6eab540719343cc8f5865f15fa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update stm32 pwm driver to support it.
Once supported across the whole family, a clean up will be done.
Change-Id: I2ed38763b706e34ea1dceea50e97ce836dd9e195
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Provide PWM driver for STM32 series F1/F4/L4.
Driver is ported on STM32Cube HAL and should support other STM32
series with minor updates.
Configuration is done so that PWM sample driver could be run on
all nucleo boards supporting PWM driver.
Change-Id: I6522a565451085df932e0eefd8404268380b5bfe
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
