This commit is about it8xxx2 platform device tree.
Add driver's binding files, and one device tree as sample.
Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
So far nRF's TIMER was used for generating PWM signal. Add support for
generating PWM based on RTC, which is sourced by 32KHz low frequency
crystal. This allows to use low frequency PWM with much lower power
consumption, because high frequency clock path can be disabled.
Don't support RTC clock prescaler, because maximum 512s period covers
most use cases. This allows to adjust pulse and period cycles to the
fact that CLEAR task event is generated always one LFCLK cycle after
period COMPARE value is reached.
Also update hal_nordic revision, as it contains updated check for PPI
channels conflict when RTC is used to generate PWM.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
So far 'timer-instance' DT property was the way to configure TIMER which
was used for generating PWM signal. Replace that by using 'generator'
phandle, so we get prepared for supporting RTC instances as PWM signal
generator.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Flash controller support is not yet ready on M4 core.
Remove the chosen declaration to make it clear.
Additionally, generate a build error if this driver is compiled
on M4 core.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Define erase and write block size for M4 side flash controller.
Additionally move compatible definition from package to soc file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Define write and erase block size for supported stm32h7 devices
Use a specific compatible string for stm32h7 devices for the flash
driver
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
Test macro DT_PROP_BY_PHANDLE_IDX_OR. There are two tests, one when
the property exists and other when the property is not set.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add power state property binding and include this property in cpu.
The pm-state attribute is a enum that matches with enum pm_state right
now the only timing attribute is the minimum residency that is the
minimum time for a power state be worthwhile.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In order to prevent user turns on the pin-mux of devices has io-pads
unexpectedly, this CL added a new device definition for host uart
device. The pin-mux of host uart interface is enabled only if we set its
status as "okay" in dts file of board folder.
The following npcx7 drivers will meet:
1. Default status property of npcx devices with io-pads such as espi,
pwm, uart, host uart and so on should be "disabled".
2. Switch pin-mux by changing status property to "okay" in dts file of
board folder.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
It is put into interrupt controller since it expands some capabilities
of existing interrupt controllers.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Define write and erase block size for supported stm32h7 devices
Use a specific compatible string for stm32h7 devices for the flash
driver
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This adds bindings for the LiteX clock control driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
SRAM base address and size are currently hardcoded in the defconfig.
This is wrong because symbols like KERNEL_RAM_SIZE and KERNEL_VM_BASE
are not currently being set. Fix this by adding the correct DTS entry.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
STM32H753xx is similar to STM32H743xx except that it has crypto/hash
hardware acceleration and the memory configuration is always 2Mbytes
flash and 1Mbyte RAM.
Signed-off-by: Petri Oksanen <petri@iote.ai>
These were found while reviewing the device tree and register addresses.
They are now the same as for the LPC55S28.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
sram4 is not connected to USB. The following sram area that is not part
of the device tree is. So the comment is removed with this commit.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Remove the zephyr,flash-controller chosen node from the NXP KW40Z SoC
series devicetree. The MCUX SDK version for this SoC is too old to work
with the Zephyr MCUX flash driver shim.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Adding support for Quectel BG95 Modem offloaded driver
to zephyr.
The driver currently implements only the
client side functions of the "socket_op_vtable", and
so cannot be used for cases where Zephyr acts as a
server. Moreover the driver only supports TCP for now.
Looking through the guides, the same driver should be
usable for BG96 (and other modems) except for the modem
boot-up sequence. Hence its named as "bg9x" instead of
"bg95".
Tested extensively with Zephyr acting as MQTT endpoint
and publishing / subscribing data to / from an MQTT
broker.
Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
Add tx/rx pl330 channel IDs for the iProc PCIe client usage.
pl330 channel 0 is allocated for Tx DMA (Device to Host write) and
pl330 channel 1 is allocated for Rx DMA (Host to Device read).
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add dma-cells property in pl330 dma binding document.
Currently only one integer cell with "channel" name is
added in order for the client to specify channel id
to be used for data transfer out of available channels.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.
STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...
The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.
Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Update nrf21540 DTS to support FEM configuration and update other pins
according to te board datasheet
Signed-off-by: Jakub Pegza <Jakub.Pegza@nordicsemi.no>
Currently there is no binding for RISC-V Core-Local Interruptor.
This patch add a simple binding.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
RISC-V clint is an interrupt controller but it has no required
properties (#interrupt-cells and interrupt-controller).
This patch just adds missing properties.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Add Atmel SAM I2C Two-wire Master Interface (TWIM). The SAM
i2c controller have specifics regs depending of operation mode
Master/Slave and the bindings are for Master only.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The YAML binding allows for a default which is used to substitute a
value if one is not explicit in the devicetree source. This feature
is mis-used when defaults are provided that are likely to be
incorrect.
Document concerns with the use of default and provide guidance for
when it can be used, what to do when it shouldn't, and noting the need
to explain the source of the default in the binding documentation.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add i2c1 interface for stm32l552xx and stm32l562xx microcontrollers
and enable i2c1 that connects to lsm6dso sensor module on the
stm32l562e_dk board.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
Add devicetree bindings for the Xilinx AXI Timer IP. This timer can
either be used as a counter or as a PWM controller.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Converts fxos8700 magnetic vector magnitude options from Kconfigs to
optional device tree properties.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Converts fxos8700 power mode options (normal, low noise low power, high
resolution, low power) from Kconfigs to an optional device tree
property.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Converts fxos8700 range options (2g, 4g, 8g mode) from Kconfigs to an
optional device tree property.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
