I2C_CLOCK_SPEED Kconfig option is DW driver specific. It does not
define I2C interface speed but rather the I2C DW module clock speed.
It is confusing for a user of any other I2C driver than DW.
This patch renames this option to I2C_DW_CLOCK_SPEED and makes it
visible only for DW I2C driver.
Change-Id: I97f57332fd5cca644eabdef0968a0b2174b885ff
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Atmel SAM family GMAC Ethernet driver is implementing zero-copy
networking. As a result it has to reserve a defined amount of RX
data net buffers before bringing up the interface. Since net buffer
pool is initialized by the network stack and this driver was bringing
the interface up in its initialization function the driver initialization
was performed, as a workaround, after network stack initialization. It
is not a clean solution. This patch fixes this by bringing the
interface up in interface initialization function. The driver itself
can now be initialized before the network stack is.
Tested on Atmel SMART SAM E70 Xplained board
Change-Id: I65886fd6db6f27a10628e393cfabd8e5f78c08ff
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Fix eth_tx function which was dereferencing a pointer before
checking that it is not null.
Tested on Atmel SMART SAM E70 Xplained board
Change-Id: Idae4cf9d9a80f6ee9f74a94dd1debe7511c5fab4
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Adds basic sensor driver support for the Maxim MAX30101 heart rate
sensor.
This driver does not yet support any sensor triggers such as the data
ready trigger, or runtime changing of sensor attributes.
Default configuration values were taken from the MikroE Hexiwear driver.
https://github.com/MikroElektronika/HEXIWEAR
Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX30101.pdf
Jira: ZEP-720
Change-Id: Ie8981e124da36a56a214f133bf9a11b9f47d60fa
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Both the string and image rendering may want to take advantage of
scrolling and sequential display capabilities. Consolidate the APIs so
that there's a single one for images (mb_display_image) and a single
one for strings (mb_display_print). Both take a duration parameter for
the per-frame duration as well as a mode parameter which specifies
sequential vs scrolling behavior as well as an optional looping flag.
Change-Id: Ia092d771e3f1b94afd494c7544dab988161c539e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Reorder the struct members for more compact layout. The current row
tracker tracks just values 0 to 2 so uint8_t is more than enough for
it.
Change-Id: I845c84aeb32d59ed0ebbd55d8b6cfda7ad19b75a
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
We don't need to store copies of the current and next image when
scrolling text, since looking up the font is just as efficient and
also consumes less memory.
Change-Id: Ia905164c5b5784afb52cb2bb38c1ab1d00817df0
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add a helper function to reset the state of the display, and make use
of it from the various public functions. This also ensures that the
timer is stopped before starting a new display routine.
Change-Id: I8a916b5b13c18b41b7fc3593e6d97e874ef117af
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add an empty column between characters of scrolling text so that the
individual characters are more easily distinguishable instead of being
back-to-back mashed together.
Also adjust the default scrolling step interval so that the character
display frequency stays roughly the same as before.
Change-Id: Idca0dc149a84f3f99b753a28ad1120ce75b97667
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
For a better clarity and minimize the possibility
of false definitions and duplicates, gather defines
by port and store the by alphabetical order then in
alternate function order.
Change-Id: Ib9febc9e6c5037a774190007120b87bf100c3fca
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
* SPIMx support for nrf52 spi interface with easy dma
Change-Id: I3221b14867924b91a9d809faf689090574f5dc1c
Signed-off-by: Roger Lendenmann <roger.lendenmann@intel.com>
Add support for I2C_2 instance on stm32lx driver
Change-Id: Iaa17305dd21f92954274ca522d30d464e0a53b7b
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
It is envisaged that this will be used by SoC or board code to make
available fixed purpose memory-mapped i/o registers to the rest of the
system which normally expects to use GPIO devices, e.g. for driving chip
select lines, LEDs or reading button states.
As such, the driver code doesn't provide a kconfig based configuration
mechanism, instead SoC/board code can hard-wire the devices it wants
with something simple like:
GPIO_MMIO32_INIT(misc_reg1, "MISC1", 0x12345678, 0xffffffffu)
Then, for example, if bit N of the register at 0x12345678 is wired up as
an SPI device chip select line, the SPI driver could be configured to
use pin N of the "MISC1" GPIO driver and not need any other board
specific code.
Change-Id: Ib02fcbab73fcf9637e25834db060fb3108626f47
Signed-off-by: Jon Medhurst <tixy@linaro.org>
On stm32 family, IP instance numbering starts from 1.
Update i2c driver to this scheme to minimize user
confusion
Change-Id: I967d5975bbbad59cd8a3a7b6dfc665955d09cc9f
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
As part of the transition to Device Tree, a temporary
HAS_DTS configuration variable, and a .fixup file per board
with symbol aliases were added.
This patch removes the cc32xx related fixup file
definitions, except for those used additionally outside
the cc32xx drivers.
Since cc32xx has DTS files, and since HAS_DTS will always be true,
it also removes the 'if !HAS_DTS' blocks from the cc32xx Kconfig
files.
Change-Id: I1c1b9f734795f523342f82ab32f2a38983812c0b
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Previously, cc3200_launchxl board was not able to show the
Zephyr Boot Banner, as that required early initialization
of the UART driver, which was done POST_KERNEL.
This patch moves the pinmux and UART driver initialization
to PRE_KERNEL_1, allowing early printk, and the Boot Banner
to show.
Change-Id: I84a7c20c1d5bdc3de150dc6bb0adebc9a2d9f5cb
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Add a new mb_display_print() API which takes printf-style parameters
and outputs scrolling text instead of one character at a time. The
existing mb_display_str() API is renamed to mb_display_string() for
consistency, and now also takes printf-style parameters.
Change-Id: I59c42bcd74c62f05ecb6d097dc808b9e5c1984c5
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Adds a simple driver to access the 5x5 LED display found on BBC
micro:bit boards. The display is so limited that no effort is done to
try to integrate with the existing console (which would likely make
the display unusable). Instead, dedicated mb_display_* APIs are added
that are specific to this display.
References:
https://www.microbit.co.uk/device/screenhttps://lancaster-university.github.io/microbit-docs/ubit/display/
Jira: ZEP-1990
Change-Id: I431b5b358b5f07592a60d3aed87eaab6ac20ce25
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows
the riscv PLIC specification as defined in the riscv privilege
architecture specification.
It provides implementation for the riscv PLIC APIs as
required by the riscv-privilege SOC Family for SOCs providing
support for the RISCV_HAS_PLIC config.
Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Rearming the riscv machine timer is done by first updating the
mtimecmp low value register. If the low value is updated with a
relatively small value, a timer interrupt can be generated while
updating the mtimecmp high value.
To avoid such a spurious interrupt to occur, disable the timer
interrupt while rearming the timer.
Change-Id: I50ab3f19554a9a8dfe70943b6da0d20be3de88dc
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This will provide the feature through Crypto API.
Change-Id: If6953a54b393544b019755ae73571effe0724e69
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Without this bit set, if we a pass ptr to a string such as:
"This is a string\n"
The DMA'ed output would be:
"TTTTTTTTTTTTTTTTTT"
Change-Id: I0186c95ddca0390596d22af2551dbfa6716a5082
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The device data structure is statically declared and referenced
on a per-controller basis during driver registration. Unfortunately,
due to using the same name (ddata) to initially declare as used
in individual functions, we accidentally referenced the main struct
by mistake due to a lack of local declaration. Let's prevent that
from happening again by using different name-spaces.
Change-Id: I9f7e5e7f95ee68d71aee70fa979e015ca2b5519e
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The STM32 DMA controller supplies streams, which in turn provide a
selection of channels. The stream number is provided by the DMA API
through it's 'channel' argument, but the sub-channel (within the
stream) is specified on an application case by case bases via Kconfig.
Change-Id: Ib5bfdb80f4d616516850787e1402164807771c5e
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Some controllers contain channels with-in channels, or in the case
of the STM32 DMA controller channels within streams. Channels
will vary depending on application, so these need to be provided
on a use-case bases.
Change-Id: I4f5fe3ec5817583b95dc7f059b5dc57f937523c4
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Fixes the fxos8700 Kconfig help indentation to be <tab><space><space>.
Change-Id: If6e9395b5d28044962ca568be5515658e7dc2627
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds sensor driver support for the NXP FXAS21002 3-axis gyroscope.
Includes statically configurable range and output data rate, as well as
the sensor data ready trigger.
Datasheet:
http://www.nxp.com/assets/documents/data/en/data-sheets/FXAS21002.pdf
Jira: ZEP-1392
Change-Id: I84587c4d5e76863245e9d045c6abb10b21b2615a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Each controller contains a number of streams. Subsequently each
stream contains a number of channels. Channels are selectable
via the stream's control register.
Change-Id: Ib75d1377cb8fc38f27e4566b275343b2ffb8da65
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Commit c0bd8a0ce4 ("api: dma: dma api update") introduced some new APIs
and deprecated the old ones. Let's move to the new API before the old
calls are completely removed.
Change-Id: I21795fa20124f8101c56b0fceb0f0d9afd96b0f0
Signed-off-by: Lee Jones <lee.jones@linaro.org>
File include/misc/sys_log.h has been moved to include/logging/sys_log.h.
Change-Id: I011ca632396b574ae7e388b47fc2ba3a58fafc7b
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Providing a new line, then an attribute on the same line as the
following closing bracket is odd. Move to something more
transitional and in line with regular coding standards.
Change-Id: I08f7cd76ca2f522a8b5b6de2e5baf94e95b5195a
Signed-off-by: Lee Jones <lee.jones@linaro.org>
It is possible to evaluate the TXE bit *before* H/W has had the
opportunity to detect that data is being processed. Therefore
we should hold off on any evaluation until TXE has initially been
set.
Change-Id: Iff26bfbe3ab419734003bf81a4cb357de83908e7
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Currently only 1 is allowed. While we're at it, let's generify the
existing entries, since they could be used by all controllers, not
just QMSI.
Change-Id: Iec5d195fff239931b21a7584eb4b642b40f95be5
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Currently the entries for STM32 UART ports are at the same level than
the top menuconfig UART_STM32. As a result they are mixed with other
configs in the "Serial Drivers" menu.
Use if/endif grammar to put these entries under a dedicated STM32
submenu.
Change-Id: If28945204b801578d29f8cce7c2370ca3c2737a1
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add support for GPIO banks I to K that can be found on some high-density
STM32F4 products.
Change-Id: I2cb65ed4d4a2282f7d17478cb1fcdd65dffe71b0
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The registration of each GPIO bank differs by only few details. These
differences can be factorized in order to create a generic registration
macro.
This has several advantages:
- Less code
- Easier to add new banks
- Less work to add support for new STM32 families
The diff stat speaks for it-self: 26 insertions(+), 92 deletions(-)
Change-Id: I674752fda5ee3caefb815ccf070a1b636b16cf85
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The PLLN multiplier can range between 50 and 432 on all STM32F4, except
on the STM32F401 where the lower bound is restricted to 192.
Fix the range property and the help text to reflect this reality.
Change-Id: I7b93e84b321f7869aaf611287344cd3e25c893c8
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Since all interrupts come in on the status line,
we only connect it for the KL2X.
Change-Id: Ia9e0d483fe68464a0eeab08c95a043260e5793b0
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Clear pending IRQ when starting and restore back the RTC1 state when
disabling sys_clock, to avoid issues when soft rebooting the device or
chainloading another Zephyr image (e.g. mcuboot).
Change-Id: I693d9168196ad2cfb8475ecfa2051eac043b1fbd
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
In prep for supporting the older KL2x SoCs that use a different SPI
block, rename the current SPI driver to DSPI to match what the MCUX HAL
defines it as.
Change-Id: I9097580df5fca649ab6fd9a38212fced0b1ea6ed
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
At the moment CC2520 configuration options are selected inside "TI
CC2520 Driver RAW channe" submenu like:
[*] TI CC2520 Driver support ----
[ ] TI CC2520 Driver RAW channel --->
Make RAW channel depends on TI CC2520.
Change-Id: I92879b7f4391f1842c012b6c03c78956e90b9441
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The fxos8700 is primarily an accelerometer/magnetometer, but it does
also include a temperature sensor. Note that the temperature sensor is
uncalibrated and can only be used when the magnetometer is enabled
(magnetometer-only mode or hybrid mode).
Change-Id: I74c4ae68c30e0f9836caa70baed44ad8956b17ea
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Declaring these as const lets the linker generate more optimal code.
Some extra care is needed with hci_ecc.c since it was overwriting the
send callback. Now the choice of send() call is done directly in the
bt_send() function
Change-Id: Iac74f5ee9bee097bbb34c11bd13d1d886700f5cc
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Support connection via SPI and keep I2C as the default.
Jira: ZEP-1698
Change-Id: I42a76131577a37429375364deb07e451107f5d81
Signed-off-by: Dario Pennisi <dario@iptronix.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Allow user to set the four last bytes of a MAC address.
By default the bytes are selected randomly but for testing
purposes we need a way to specify the address in advance.
Change-Id: Ic9820a8026b327d1ee5025ab77fdc77f5778de67
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Networking stack has split one global DATA pool to RX and TX DATA pools
and also added net_buf pool support to each context. Update the driver
to support this new design. Since the GMAC TX descriptor list has a fixed
size but the number of TX DATA buffers is no longer limited updating the
TX descriptor list has to be guarded by a semaphore.
Tested on Atmel SMART SAM E70 Xplained board
Change-Id: I181e1cdd183e173b85d5d1711b6e78cd5165666d
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
It is possible that the slip->last pointer is not set during
the startup of the slip driver if we receive some garbage bytes.
This in turn caused memory to be overwritten in random places.
Jira: ZEP-1737
Change-Id: Ia2ce193b81a8f707b7ca63497d497ea70699bb32
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
No need to always look through all the network interfaces
when receiving packet as we support only one interface and
it is always the same one.
Change-Id: Ic0bfabc8409160352081cac1a6c3dbbfa35fe390
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
The current state of affairs will not allow to set a MAC address and
thus will initialize a random MAC address.
However, when we are in a situation where we are trying to interface
Zephyr OS QEMU VMs with physical targets for testing, this is not
practical. We need to create a macvtap interface, on which we need to
set the MAC address of the Zephyr OS SLIP device so packets can be
routed. There is no way to guess which random address is going to be
used, and there is no practical way to query it.
So this patch adds a CONFIG_SLIP_MAC_ADDR config
setting. slip_iface_init() is changed to take the code from
slip_get_mac() for initializing the MAC address (which should be
happening there anyway) and if CONFIG_SLIP_MAC_ADDR is set, it takes
that one -- otherwise goes to generate a random one.
Change-Id: I55a68f2743604f310d41c934783eca82084d7e94
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Add few nop instructions to allow the DMA controller settle,
It takes time after starting the transfer to access the DMA
controller registers, so a few cycles are added, the minimal number
of cycles needed has been calculated using tests results on c1000
development board.
Jira: ZEP-1803
Change-Id: I1f8e8478f0350e1b6e4dd596b783dc4babc2d02b
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This commit adds missing RAW mode device to the driver.
Change-Id: I9ee9c41bc94b0ae202613ef707030033b46df1de
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
The PHY debug code is useful while working specifically with the PHY
state machine, but in general the frequent, periodic nature of the
output is a hinderance. Turn down the verbosity, leave a local define
available for anyone who specifically needs to see the PHY state
machine debug.
Change-Id: I40e59b6df5c29702813d3a554ea9e795a3761c65
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The enc28j60's reception routine requires a timeout
for a buffer assignation. The timeout is configurable
to allow a per application fine tuning.
The effect that K_NO_WAIT currently has is that there are frames
lost everytime that a buffer is required and there are none
available.
Jira: ZEP-1169
Change-Id: Ia18736fd85daee51fe1c2304977209cc7f0038b5
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
The code used net_nbuf_get_reserve_{rx|tx}_data() function to
allocate a fragment. Instead of that low level function, use
net_nbuf_get_frag() instead. There are few places this is not
possible or is too big change like in few test programs.
Change-Id: Ied7e2b7db352de998b200ffa6ff82471bfa5ebe3
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If we receive lot of packets, it might happen that we exhaust
all the DATA buffers in the system. This would prevent from
us sending anything to the network.
Change this by splitting the DATA buffer pool into RX and TX
parts. This way RX flooding cannot consume all DATA buffers
that needs to be sent.
Change-Id: I8e8934c6d5fdd47b579ffa6268721b5eb3d64b6d
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Provide a configuration option for promiscuous mode.
Promiscuous mode provides a convenient workaround for ZEP-1673 however
it generates significant demand for RX buffers on a loaded network.
Add a configuration option to conveniently enable / disable.
The Kconfig defaults promiscuous on to workaroudn 1673, once that
issue is resolved the default logic on NET_IPV6 will be dropped.
Change-Id: I6929aca70d7bd88ce88c65d6654d664ea6653b66
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Basic Watchdog driver for Atmel SAM family MCUs. Currently only
disabling the watchdog is supported.
Tested on Atmel SAMV71 Xplained Ultra Evaluation Kit.
Origin: Original
Jira: ZEP-1684
Change-Id: I8f717c7f53aa290c944b7935e0570c2a6f53956e
Signed-off-by: Souvik K Chakravarty <souvik.k.chakravarty@intel.com>
Provide a random driver wrapped around the MCUX TRNG driver.
Change-Id: Icbd7ab587aa18ecbd7eae52290aaa5d8ee504cf2
Origin: Original
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
MCUX contains more than one type of random number generator,
so refrect this in config and file names.
Change-Id: Iba4482a1ae41f35d471686f8b159c113147c4df8
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Current users of sys_bitfield*() are bending over backwards to cast
what is most of the times a pointer into an integer.
Bitfields can be better described with an void *, so
uint{8,16,32,64}_t or any other container can be used. Most
sys_bitfield*() operations, by extension, can do the same. Note void *
has byte arithmetic, like char *.
This change will also make it implicit, for any future split of the
address space between virtual (what the SW is seeing) and physical
(what the HW is seeing) way clearer, as the functions dealing with
physical, non directly referentiable/mappeable addreses to use an
integer type, like mem_addr_t.
- include/arch/ARCH/*asm_inline*:
- sys_bitfield*() all modified to take 'void *'
Note 'void *' arihtmethic is byte based, which makes some things
easier.
- include/sys_io.h:
- introduces DEFINE_BITFIELD
- update docs
- tests/kernel/bitfield: remove all the cast contortions, use DEFINE_BITFIELD
PENDING: update other TCs
- include/arch/nios/nios2.h, drivers/interrupt_controller/ioapic_intr.c:
remove cast contortions
Change-Id: I901e62c76af46f26ff0d29cdc37099597f884511
Jira: ZEP-1347
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
These are more consistent with naming used by other ports (uppercase,
short), and some existing software relies on them to be exactly those.
This change is a follow up to the discussion on the Zephyr mailing
list, calling to establish consistent naming conventions for Zephyr
devices, and is a small step in that direction.
Change-Id: I013b0505b579c6337aeb6fbef2423216ca6cf046
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
To secure correct signal levels on the pins by the UART when
the system is in OFF mode, the pins must be configured in
the GPIO peripheral as described in nRF5 Product
Specification.
UART Pin, Direction, Output Value:
RXD, Input, NA
CTS, Input, NA
RTS, Output, 1
TX, Output, 1
This commit sets the RTS line to a initial value of 1.
Change-id: I5147fe58033f42c979b9354798b6fd13d78f7f71
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
To avoid glitches in the lines, set the line to the pull specified
before actually changing the line's direction (in/out) so that no
unexpected pulses are generated.
Change-id: I4fe133c5b82f2a1bfa473341612c2c7eca9027b8
Signed-off-by: Krzysztof Chruściński <Krzysztof.Chruscinski@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Refactor the PHY state machine and add support for explicit start and
stop.
The stop implementation remains partial, the state machine will enter
a disabled state but will not actual attempt to power down the PHY.
This is deliberate, while implementing this it has become apparent
that issuing a PHY power down command is an effective way of bricking
frdm-k64f boards, hence explicit power down deliberately disabled
until the issue is properly understood.
Change-Id: I846a51b0ac48feed35d260cf20b50f4f1ac59298
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Add the link type to net_if_set_link_addr() call. This fixes the
driver after changes introduced in
4eb2020055.
Change-Id: I72475a055ac805524b4b0f0c2380513e8f041368
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
Some fixes where needed to get PLL2 source of PREVI1 functional.
Compiled ok with following configuration:
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK=y
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2=0
CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER=8
Jira: ZEP-1758
Change-Id: I5ddfaef1b44c4c4e5e6adedc158a1c9092bc8df5
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some GPIO ports activation where missing since not used
on available soc/boards.
Since stm32 family increases, activation of these ports
should be made available.
Jira: ZEP-1551
Change-Id: I612d135b28ef255bc771599e33796671ff81d0ac
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We need to account for the interrupt happening in the middle
of the calculation.
Issue: ZEP-1546
Change-Id: I193534856d7521cac7ca354d3e5b65e93b984bb1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Using net_nbuf_unref to release the net_buf so that we can
debug the allocations more easily. It is ok to use the original
net_buf_unref() too, we just miss some important net_buf
housekeeping information if done like that.
Change-Id: Ieb7b39ed525bfc46eb5c07a01f2a3a75fdbeb9fd
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If slip_input_byte fails to get buffer for the first byte then no point
of saving later bytes and send it to upper layers. Final packet will be
incomplete and upper layers will discard it. Consider incoming bytes
only after successful buffer allocation on first byte, otherwise silently
ignore it.
Change-Id: Ie16d0df0c608d1644d39f66900252a340051c012
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
No functionality changes. Added more comments and used switch cases
for more readability.
Change-Id: I9396270d7368d9b0c923a88f90b44129a1d69cbc
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
The interface L2 address type is set at the same time as the
L2 address is set to the network interface. This is most
convinient place to set the address type.
Change-Id: I712d7357d075959eb79df3463141cfbc6d163a74
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This commit adds a driver for nRF5 802.15.4 radio. This driver
is a wrapper for the driver provided by ext/hal/nordic/drivers.
Change-Id: I20ee4aff3d1b994c621ba8eaab208d15d85e4c01
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
The interrupt processing of MCR20A was flawed and complicated.
This patch simplifies the handling of interrupts and reduces
the number of necessary SPI transfers.
Minor fixes:
- use mutex for the PHY access control
- remove unnecessary mcr20a_mask_irqb calls
- do not read RX_FRM_LEN twice
- increase timeout for sequence synchronization semaphore
if the log level greater than 1
- enable only the Sequence-end (SEQIRQ) interrupt
- fix magic in NET_DEVICE_INIT
- make the timeout values dependent on the log level
Change-Id: Ib3f64a092ffba91c80ff6e1d5cec995ab9d40bfb
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Fixes an unlikely issue that could arise if the RTC handler in the nRF RTC
driver was blocked for more than one sys tick interval. This could lead to
_sys_clock_tick_announce() being called with more than one sys tick when the
kernel did not expect it.
Jira: ZEP-1763
Change-ID: I5608fca6f0ac97a17c1ce452c1c5c67696a49a9a
Signed-off-by: Øyvind Hovdsveen <oyvind.hovdsveen@nordicsemi.no>
The LOAPIC driver was doing this in a way susceptible to a very
nasty race condition: the CCR register could reset and be readable
before the associated interrupt could be delivered.
This resulted in a small window of time where CCR was reset, but
accumulated_cycle_count not updated, causing some calls to
k_cycle_get_32() to appear to jump backwards in time.
Just use the x86 TSC for these cycle timestamps. A divisor may be
provided in cases where the CPU clock speed is some multiple of
the bus speed. Modern x86 CPUs do not change their TSC rate even
when adjusting cpu frequency, so this should be a reliable timing
source.
Issue: ZEP-1546
Change-Id: I441bd8e32af866587a91f306e89e3fa0ece512b5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's possible the timer interrupt could occur when performing the
computation, resulting in incorrect values returned.
It's still possible for bad values to be returned if the function is
called with interrupts locked, but that is only fixable with a second
timer source.
Issue: ZEP-1546
Change-Id: I16d5b04c3e32377f7249eb4fb1bf2f7c22bd0836
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Some files made it through review process with full license header.
Change-Id: I2722b127c40b4b19500042c12e4fde85a165bae9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is a reworked version of the previous RTC driver. The main
changed is related to the handling _timer_idle_exit() on non-RTC
wake-ups. The previous version didn't announce the elapsed time
to the kernel in _timer_idle_exit(). Additionally, the driver now
makes sure never to announce more idle ticks than the kernel asked
for, since the kernel does not handle negative deltas in its timeout
queues.
Change-Id: I312a357a7ce8f0c22adf5153731064b92870e47e
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
Signed-off-by: Øyvind Hovdsveen <oyvind.hovdsveen@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Some arches may want to define this as an inline function, or
define in core arch code instead of timer driver code.
Unfortunately, this means we need to remove from the footprint
tests, but this is not typically a large function.
Issue: ZEP-1546
Change-Id: Ic0d7a33507da855995838f4703d872cd613a2ca2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On Nios II the same timer peripheral IP block can't function
as a periodic system timer and a high-resolution timestamp source.
A second timer instance with different configuration is required.
Until that is implemented, just return the accumulated cycle count.
Issue: ZEP-1546
Change-Id: If3dcebdc60334bf3aa0ab45ccd82f1b2531b6bc1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
There are race conditions trying to coordinate the value between
the accumulated_cycle_count (updated at interrupt time) and
trying to compute the delta from the last interrupt using the
mtime registers. An unlucky call could result in the timestamp
appearing to move backwards in time.
the 'mtime' register isn't reset at every interrupt. Since we just
want a cycle counter, report its raw value.
Issue: ZEP-1546
Change-Id: I9f404b33214d6502fea47374fcf0ecbf84ef8136
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This driver currently only handles memory-to-memory transfers.
TODO: Add support for all types of transfers.
Change-Id: Ic9787dcca919a58fb11b48c9f6b6b371db88c3ea
Origin: Original
Maintained-by: Zephyr
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Adds a driver for Atmel Crypto Authorization solution
ATAES132A crypto device.
The driver supports the following functionality.
- AES CCM encryption, decryption and authentication
- AES ECB block operation.
The driver requires an I2C device to access crypto device registers.
Jira: ZEP-1387
Change-Id: I60aa8f3b069b703d4f83d866d28391625bb9ac13
Signed-off-by: Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
Shim layer interfacing between crypto APIs and TinyCrypt
library. Currently facilitates only a subset of TinyCrypt
features/algorithms.
Jira: ZEP-509
Change-Id: I7fe6b9d86df016d92d717378d08a1ab09caafb31
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
When a GPIO pin is configured, the shim driver will first read the
current values in the controller registers to keep the other pins from
changing their configuration. After that it sets the bits for the
corresponding pin accordingly.
When the flag to enable interrupts is passed to the function, the
corresponding bits are all set properly, but no changes are made if
interrupts are not requested. This makes it impossible to disable
interrupts for a given pin once they've been enabled.
Fix it by always resetting the interrupt enabled bit when they have not
been requested. Other values can be left untouched as they won't have
any effect.
Jira: ZEP-1717
Change-Id: I30e97bb06d966291e23d0c66ddf39bce615c287b
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Requesting a flash_write with a length of 0 results in a flash
position being written. Instead we should return 0 unless there is
some other input parameter that is invalid.
Change-Id: Ife6e6e2314bbee2bde7d0b69db3122ca00c361e0
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
This is a workaround for lack of driver API support for multicast
management. So, instead we want to receive all multicast frames
"by default", or otherwise basic IPv6 features, like address
resolution, don't work. On Kinetis Ethernet controller, that
translates to enabling promiscuous mode. The real fix depends
on ZEP-1673.
Change-Id: I98a27584be65bdc405de005383eb30bad2a7fcfc
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Add basic PHY management sufficient to detect link up, link down and
auto negotiated link speed / duplex. The PHY driver is implemented as
a state machine that executed in the system work queue. The
implementation is non blocking, using the MII interrupt to capture the
completion of read and write events.
This PHY management should be fairly generic. In the future, it may be
beneficial to pull this code out as a standalone PHY driver for use
with other ethernet drivers.
JIRA: ZEP-1674
Change-Id: I3dcb5c14982ef4b40591fcf10d84840b8a2558e5
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This driver was written for v1.5 before the introduction of the function
_sys_clock_final_tick_announce. At that time _sys_idle_elapsed_ticks was reset
to 0 automatically. Now that it is reset by the new function, the driver needed
to be fixed.
Change-Id: I039b4dbacb691aaf992b37e44404abd19a54a833
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
This is needed by next commit as some assembly files handling interrupts use
some options from this file.
This file is not included in next commit to separate code and build system
aptches.
Change-Id: Iff3a8019362599beb0c0058c3169480fa5183c1c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
These were reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: I10d04c2949ad2a390d4c1159d2342c73108a58b7
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
This commit brings code size optimization as suggested by Christer
Weinigel review during review of initial commit for this driver.
It also cleans up useless definition in header file.
Change-Id: Ibeaa2e51570dff21825c60c30ba83d939b31d938
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After activation of cube based driver support on L4 and F3 series,
this commits performs the clean up of F3 and L4 relative code to
native clock control drivers.
Indirectly, it makes pwm driver supported de facto on F3 series
Change-Id: Idac17103a9b5ef6eab540719343cc8f5865f15fa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction and activation of STM32Cube LL based driver on
F3 and L4 series, this commit removes the no more needed code for
native driver for these soc.
Change-Id: I266d1a3fc4b464cee34b1cc1a1a333c5bf923e41
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update stm32f3xx flash driver to support it.
Clean up will be done afterwards.
Change-Id: I3260bb063f714fa29adbc71d8036f20479a99b34
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update stm32 pwm driver to support it.
Once supported across the whole family, a clean up will be done.
Change-Id: I2ed38763b706e34ea1dceea50e97ce836dd9e195
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update stm32 i2c_lx driver to support it.
Clean up will be done in a following commit.
Change-Id: Ie5059bf4122d65fab1a663a5b00e0d761850a49d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use of SECONDARY in DEVICE_AND_API_INIT is now deprecated and should
be replaced by POST_KERNEL
Change-Id: I543ae70e493527e75b4a4bcb9191475065b49166
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update stm32 serial driver to support it.
Once supported across the whole family, a clean up will be done.
Change-Id: I7100bc699e7918c8be71d58091da1860ab734e25
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update pinmux driver to support it.
Once supported across the whole family, a clean up will be done.
Change-Id: Icc20816377f3a09f516a743462c92696a1fead3a
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update GPIO driver to support it.
Once supported across the whole family, we clean up will be done.
Change-Id: If50cb580cb01dc1d38557e54f19a8260feaa504e
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new clock control driver aims at providing a lightweight
generic driver to the whole stm32 family.
Driver is based on LL Cube API and hence is for now available
only for STM32 supporting this API: stm32f3xx and stm32l4xx.
Other families should be supported soon.
Once globally supported, this unique driver will also help
reducing the impact of stm32 clock control heterogeneity in
other drivers.
Change-Id: Id15a8d0d44f03809b2907ef10d6877700459e674
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch adds the base DTS support for the KW41Z Freedom board. The
initial set of changes include SRAM, FLASH, IRQ controller and LPUART
support.
Change-Id: Ic68c4959ddad0c5cfe70d5576a0e58372b93ec9d
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
This patch adds DTS support to the ARM CMSDK UART driver. The DTS
currently specifies the IRQ, IRQ PRIO, and base address of the port.
Change-Id: I8e5bc81c013958be4297d563495bf126b53a83a9
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds device tree support to the STM32 UART driver. The base
address, interrupt, and interrupt priority values can now come from DTS.
Change-Id: I3c383da8b200037601ecb2dc087f99ef103761bb
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch ifdef's out information that would be redefined by
information generated from DTS. This patch also fixes up the serial
drives to work properly with the DTS generated information.
Change-Id: I912ccf35be23c107705a4866e5a68b3b51154ffa
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support and related files for the NXP Kinetis
platform. The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms. The YAML files provide the definitions of
the contents of the DTS nodes.
The Kconfig changes were put in place to allow for the conversion of
existing drivers. Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.
Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit removes unnecessary CONFIG_SYS_POWER_DEEP_SLEEP protection
in shim drivers as QMSI 1.4 has introduced empty context save/restore
functions that can be called in Quark D2000, therefore keeping common
code at the shim driver level for Quark SE and D2000.
Change-Id: Ia2a466327f999668c6511c0193014e9151bff6ae
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
Use new device name for SPI device
Jira: ZEP-1704
Change-Id: Iec39468bbef54423af2b3a681dd4ae1eee866d1e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update the qmsi dma shim driver based on the new dma api
interface.
Recently, a RFC was posted to update the dma api. The update
to dma api interface was already posted. This change is to
update the dma qmsi shim driver based on the dma api change.
It is using the new data structures and new api function names.
Jira: ZEP-873
Change-Id: If9a772c5ff1c2b10fca05172c48f75223bbf940e
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Enabling the riscv_machine_timer driver by default for riscv32
causes compilation issues on riscv32 boards (like zedboard_pulpino)
not supporting it.
Boards supporting the driver enable it via their respective
config file.
Change-Id: Ieb0d25fa339834fd386ae2725f40b6b7b72dc52b
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This is one the series patches that simplifies the driver code by
using the IS_ENABLED macro. This removes the need of the const
variable and the wrapper functions on semaphore APIs.
Jira: ZEP-1251
Change-Id: Ic2df5d04966d2a066478ca3e119f76d24fc4dfb3
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
This is one of the series of patches that simplifies the driver
code by using the IS_ENABLED macro. This removes the need of the
const variable and the wrapper functions on semaphore APIs.
Jira: ZEP-1251
Change-Id: I84a09a0aaa3a00452d8c2b4bca7be0f6b2015218
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
This is one the series patches that simplifies the driver code by
using the IS_ENABLED macro. This removes the need of the const
variable and the wrapper functions on semaphore APIs.
Jira: ZEP-1251
Change-Id: I59802cf9f482337656b0fdc4b272f3b1ddc6cbda
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
This commit removes the aonpt interrupt masking/unmasking needed after
wake up as that functionality is now available in QMSI 1.4. The QMSI
save/restore functions are called instead.
Change-Id: I61a4a6952e959d0834904bbc8e1eb98092ae4b1c
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
This commit removes the RTC interrupt masking/unmasking needed after
wake up as that functionality is now available in QMSI 1.4. The QMSI
save/restore functions are called instead.
Change-Id: I15b5063fa64c71b125edd2c709410b5ae655032e
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
Several GPIO device drivers support only one of the two possible
access_op modes and return an errno error code for the mode they do
not support. Use the same errno code across all drivers.
Change-Id: Ic01ce9dee7fb2405d254c60cebee22053c803270
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Several GPIO drivers detect an out of range pin number and return an
errno error code. Use the same errno code across all drivers.
Change-Id: I0e2949432d6845d12c37064c78f9c228b8e8e45a
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Several gpio drivers consider GPIO_INT with GPIO_DIR_OUT to be illegal
and return an errno code. Use the same errno code across all drivers.
Change-Id: I1594df0cfdf96194685c83c34dff36261896f2de
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This flag is no longer necessary and TICKLESS_IDLE will be
enabled by default if SYS_POWER_MANAGEMENT is enabled.
Jira: ZEP-1325
Change-Id: Ic6cd4b8dc0a17c6a413cabf6509b215a4558318d
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Update the builtin QMSI code to 1.4 (RC2).
The below shim drivers were updated for API or interface changes:
- aio
- counter
- i2c_ss
- rtc
- wdt.
Also, arch soc specific power management code were updated.
Jira: ZEP-1572
Change-Id: Ibc8fae032a39ffb2c2c997f697835bc0208fd308
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
If subcription was found within the subscription list,
we have check if remains identical subscription
from the next node.
Otherwise none unsubscription is realized.
Change-Id: I38132d7c80575801885b8057902f3d4666b08aea
Signed-off-by: Jonathan Gelie <jonathanx.gelie@intel.com>
This commit changes the net_buf getter functions in nbuf.h
by adding a timeout parameter. These function prototypes
are changed to accept a timeout parameter.
net_nbuf_get_rx()
net_nbuf_get_tx()
net_nbuf_get_data()
net_nbuf_get_reserve_rx()
net_nbuf_get_reserve_tx()
net_nbuf_get_reserve_data()
net_nbuf_copy()
net_nbuf_copy_all()
net_nbuf_push()
net_nbuf_append()
net_nbuf_write()
net_nbuf_insert()
Following convinience functions have not been changed
net_nbuf_append_u8
net_nbuf_append_be16
net_nbuf_append_be32
net_nbuf_insert_u8
net_nbuf_insert_be16
net_nbuf_insert_be32
net_nbuf_write_u8
net_nbuf_write_be16
net_nbuf_write_be32
so they call the base function using K_FOREVER. Use the
base function if you want to have a timeout when net_buf
is allocated.
Change-Id: I20bb602ffb73069e5a02668fce60575141586c0f
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This commit changes Kconfig prefix for ieee802154 drivers to
IEEE802154_*. This is done for consistency with config prefixes
used in other subsystems.
Change-Id: Ibbb4d96d2b748f4f13135bde85304ec34c5a90a6
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
The driver was using net_buf_unref(). This technically works
ok but debugging the network buffer allocations is more
difficult if done like this.
Change-Id: If3453a49337c7a359c8af22cfdf331fccc697af5
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This commit splits 802.15.4 drivers configuration into separate files.
Change-Id: Ie1bed862e8f4248240fef18bc211d0ee8ca1493c
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
The DW i2c driver chooses to return -EPERM following a PCI error in
driver configuration. This seems an odd choice. All of the other I2C
drivers return -EIO for general failures detected during driver
configuration.
Switch the DW driver from EPERM to EIO.
Change-Id: Ia4f96386620319736ae4c09212b0a05ea38169b1
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The I2C drivers handle an empty list of I2C messages inconsistenty.
There are two different behaviours, one set of drivers dectects a
requests to transfer zero messages and return -EINVAL while the other
group simple transfer no data and return success.
Adopt the latter behaviour consistently across all drivers. Update
the i2c.h API documentation to reflect this behaviour.
Change-Id: I427fc1b0e18ddc04b7b59c294e0240b3d6ca4073
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Subscribe value is set to zero before calling notify callback,
to distinguish a subscription failure from an unsubscription
on disconnection (when flag BT_GATT_SUBSCRIBE_FLAG_VOLATILE is set).
Change-Id: Ia91220492d82041b2c385bf88a15180387e7a483
Signed-off-by: Jonathan Gelie <jonathanx.gelie@intel.com>
Some application protocol required non-persistente subscription
across connection even in bonded case.
Flag BT_GATT_SUBSCRIBE_FLAG_VOLATILE specify if subscription
must be remove during disonnection.
Change-Id: I1bc2bbbb4bc86f58905e44a7eb267ca0871f2fdb
Signed-off-by: Jonathan Gelie <jonathanx.gelie@intel.com>
Implement the missing port read and write behaviour.
Change-Id: I0928379eddf81d806a0ae6b75a1ea2993c3a28ff
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Adjust the implementation of gpio_pin_read() to return 0 or 1 rather
than 0 or 2^pin. This ensures consistent behaviour with other gpio
device drivers, and conforms to the behaviour documented in gpio.h by
the previous patch.
Change-Id: Ia02aa68105a406f355d16a3f9b0550f948658483
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The subscriptions callback may free or reuse the subscription so all
instances that where this could happen need to safely fetch the next
element which is why this changes switch to use sys_list_t as it has
SYS_SLIST_FOR_EACH_NODE_SAFE.
Change-Id: I37d51f27116ea0c057b560924a9416676477597b
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Reduce the pressure on the common RX buffer pool by reusing HCI
command buffers also for the Command Status or Command Complete
response to them. This also implies removing the existing Kconfig
variable for the command buffer sizes since the size is also dependent
on maximum Command Complete event sizes. Instead, reuse the RX buffer
size also for HCI Command buffers.
Change-Id: I006b287d64a0c9ca40de741aa9a424a49a927385
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
A subsequent patch will start reusing HCI command buffers for
receiving the response, so the distinction of received vs sent data
headroom would just make the code unnecessarily complex. Instead, just
merge these two variable into a single one.
Change-Id: I31d846331939f1a2270df7ed0c75112825e16493
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
If we are low on RX buffers and receive an LE Advertising Report or a
BR/EDR Inquiry response we should just discard this. If we don't
discard the event we increase the risk of deadlock where the RX
interrupt is enabled but bt_recv() is doing a synchronous HCI command
sending, i.e. waiting for a cmd_status/cmd_complete (which will never
come since the RX interrupt is disabled).
Change-Id: I6266625c9790d68bcf8e8718c8c36f127946c4c6
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add sensor sample ready check before fetching the sample.
Otherwise, invalid value will be returned.
Jira: ZEP-1532 ZEP-1358
Change-Id: I570151c8ae93fbb744dac857521f596fd63806a6
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.
The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.
Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This is a zero-copy networking implementation of Ethernet driver.
Limitations:
- one shot PHY setup, no support for PHY disconnect/reconnect
- no support for devices with DCache enabled due to missing
non-cacheable RAM regions in Zephyr.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1492
Change-Id: Ib944f91193efbd12c1142b0bcf1f635388bf1b87
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added basic USART driver for Atmel SAM MCU family. USART is a very
comprehensive module, currently only basic features sufficient to
support printf functionality are implemented by this driver.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ia9710e4069243fb6c30de45953dfc1fe1266b63a
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
I found that I was not getting the i2C interrupt.
When CONFIG_I2C_0_IRQ_DIRECT=y, it is acceptable to just
pass the constant to irq_enable.
See ZEP-1651.
Change-Id: I10955e6d6fe5fdd2dda916c92c8bc8a2e871f41a
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Replace _ScbExcPrioSet with calls to NVIC_SetPriority as it handles both
interrupt and exception priorities. We don't need to shift around the
priority values for NVIC_SetPriority.
Jira: ZEP-1568
Change-Id: Iccd68733c3f7faa82b7ccb17200eef328090b6da
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds a shim layer around the mcux lpuart driver to adapt it to the Zephyr
serial interface.
NXP has multiple uart hardware blocks that implement different features
and have different register maps. The k64 has a uart block called
'uart', while the kw41 has a uart block called 'lpuart' (low power
uart). The MCUXpresso SDK provides separate drivers for each type of
uart block but with similar software interfaces. As a result, there are
also separate shim drivers in Zephyr. There is a 1:1:1 relationship
between hardware block, mcux driver, and mcux shim driver.
Because we now have two mcux shim drivers for the uart interface, a new
naming convention is created:
<interface>_mcux_<hw block>
Where <interface> is the name of the Zephyr interface, in this case
'uart'. This convention is not new.
<hw block> is the name of the NXP hardware block, in this case 'lpuart'.
This is the new part, and distinguishes different hardware blocks
for the same interface.
Change-Id: I3a80b9bffa116bbb2b02ee950d4bdd79a19a4edc
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The newer version of mcux changes its flash api slightly, so update the
Zephyr shim accordingly.
Change-Id: I0c974fc3e82b9f40372c636f0b805ed143be2198
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
