These libraries are unlikely to be uesd by GCC port and thus should not be in
a generic make file. Moved to specific toolchain make file.
Change-Id: Ib585b87700e409d678f7a5cb60cff67b6022ab05
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
Master branch changed requirements for license headers while this
branch has been in development.
Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Provide generic support for running zephyr kernels on xtensa QEMU and
map D_233L SoC to dc233c QEMU core.
Change-Id: Ie804588f750213a7cc54dbc95c86ee4d62ba1ea5
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.
Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
This replaces the hard-coded vector table, as well as the
software ISR table created by the linker. Now both are generated
in build via script.
Issue: ZEP-1038, ZEP-1165
Change-Id: Ie6faaf8f7ea3a7a25ecb542f6cf7740836ad7da3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a new mechanism for generating interrupt tables which will
be useful on many architectures. It replaces the old linker-based
mechanism for creating these tables and has a couple advantages:
1) It is now possible to use enums as the IRQ line argument to
IRQ_CONNECT(), which should ease CMSIS integration.
2) The vector table itself is now generated, which lets us place
interrupts directly into the vector table without having to
hard-code them. This is a feature we have long enjoyed on x86
and will enable 'direct' interrupts.
3) More code is common, requiring less arch-specific code to
support.
This patch introduces the common code for this mechanism. Follow-up
patches will enable it on various arches.
Issue: ZEP-1038, ZEP-1165
Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In order to set breakpoints after waking up from sleep,
it is needed to save DR0/DR1/DR2/DR3 and DR6/DR7.
As DR4/DR5 are reserved or mapped to DR6/DR7, they are not saved.
Patch2 : Added compile time checks for debug build or soc_watch
build for Intel Energy analysis.
Patch3 : Avoid clobbering of edx.
JIRA: ZEP-1681
Change-Id: I62fbedca16953d57196420ecae4fb93c785bb4a5
Signed-off-by: Sarath R Nair <sarath.nandu.ramachandran.nair@intel.com>
This patch moves the include for the generated_dts_board.h inside of
the include/arch/arm/arch.h file. This was done to simplify the
includes required for files. Only two files will include the dts
generated include file directly: arch.h and the linker.ld
Change-Id: I2614f4fd4eeed2ab635a3264d7dac8b83f97b760
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We now use CMSIS for ARM Cortex-M SoCs so we can remove the last bits of
scs and scb.
Jira: ZEP-1568
Change-Id: I0c7c45b0321dc402ed594e9faffb5109922edcf0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Coverted:
_ScbMemFaultMmfarReset
_ScbBusFaultBfarReset
_ScbUsageFaultAllFaultsReset
To use direct CMSIS register access.
Also removed scb.h and references as there is no longer any code in it.
Jira: ZEP-1568
Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The previous code incorrectly used the value 0xfe to clear the mem and
bus faults. It attempted to handle the address register valid bits
separately, but reversed the bit order.
Jira: ZEP-1568
Change-Id: I240d072610af9979ca93c0081ed862df08929372
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Converted access to CFSR MMFSR, BFSR, and UFSR to use direct CMSIS
register access when printing out the values of those registers.
Jira: ZEP-1568
Change-Id: I7969bb81346327637140ec23d91422a6bfaef032
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Coverted:
_ScbBusFaultAddrGet
_ScbMemFaultAddrGet
To use direct CMSIS register access
Jira: ZEP-1568
Change-Id: Ic49b3ac3fc4fb63d413f273569c77f6539e4e572
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Pin number should be decremented by 8 if the pin
refers to the GPIOx_AFRH register.
Change-Id: I76e960f3b4adc3c2139ef5a88f15dbe98603228e
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native F3 Clock control driver.
Change-Id: I6f3ee44adb09adc52927eb4b05f8a829665eb96d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native L4 Clock control driver.
Change-Id: Ic0408d5f5ec66651d46d13dfaf447da2666367cd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32f3x soc.
Clean up will have to be done afterwards.
Change-Id: I20480579f12a6fc1f1f6a51589981ac3f1d63ef0
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32l4x soc.
Clean up will have to be done afterwards.
Change-Id: I979a4169148c5fe5a0693d182d2d17f9ffaf1c77
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch adds the base DTS support for the KW41Z Freedom board. The
initial set of changes include SRAM, FLASH, IRQ controller and LPUART
support.
Change-Id: Ic68c4959ddad0c5cfe70d5576a0e58372b93ec9d
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
This patch adds DTS support to the ARM CMSDK UART driver. The DTS
currently specifies the IRQ, IRQ PRIO, and base address of the port.
Change-Id: I8e5bc81c013958be4297d563495bf126b53a83a9
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the base DTS support for the V2M Beetle board. The
initial set of changes include SRAM, FLASH, and IRQ controller support.
Change-Id: I06685622b9c57ac358544c71350074ce06e3371e
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds all the necessary changes to enable use of DTS for
generating required build information.
Change-Id: Ia476fbb14c7d9d6b9db3340c73f599556a880da3
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch ifdef's out information that would be redefined by
information generated from DTS. This patch also fixes up the serial
drives to work properly with the DTS generated information.
Change-Id: I912ccf35be23c107705a4866e5a68b3b51154ffa
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support and related files for the NXP Kinetis
platform. The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms. The YAML files provide the definitions of
the contents of the DTS nodes.
The Kconfig changes were put in place to allow for the conversion of
existing drivers. Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.
Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support for using device tree configuration files for
configuring ARM platforms.
In this patch, only the FLASH_SIZE, SRAM_SIZE, NUM_IRQS, and
NUM_IRQ_PRIO_BITS were removed from the Kconfig options. A minimal set
of options were removed so that it would be easier to work through the
plumbing of the build system.
It should be noted that the host system must provide access to the
device tree compiler (DTC). The DTC can usually be installed on host
systems through distribution packages or by downloading and compiling
from https://git.kernel.org/pub/scm/utils/dtc/dtc.git
This patch also requires the Python yaml package.
This change implements parts of each of the following Jira:
ZEP-1304
ZEP-1305
ZEP-1306
ZEP-1307
ZEP-1589
Change-Id: If1403801e19d9d85031401b55308935dadf8c9d8
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Without this patch, the final linker script had a memory region defined
as:
RAM (wx) : ORIGIN = 0xA8006400, LENGTH = 55*1K - 0x20 +0x4
resulting on the wrong RAM length. Fix BSP_SHARED_RAM_SIZE definition
so the sum is always processed first.
Change-Id: I16b93adbaf27bb84b6e5d1ac433ef80f854b218c
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Arch-specific stuff shouldn't be in the toplevel Makefile,
forthcoming patches will soon introduce special interrupt
handling logic for other arches.
Change-Id: Ib5a86cbdf5b32ecfce9e5e234f7cbea2bc3ce9c1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This private data structure now no longer introduces a typedef or
uses CamelCase. It's not necessary to specify the size of extern
arrays, so we don't need a block of #ifdefs for every arch.
Change-Id: I71fe61822ecef29820280a43d5ac2822a61f7082
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit removes the local implementation of enter_arc_state, where
the ARC is instructed to sleep, using instead the QMSI 1.4 functions.
Change-Id: Id489ad53851be50fc5e50add698891fcfaef3abe
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
This flag is no longer necessary and TICKLESS_IDLE will be
enabled by default if SYS_POWER_MANAGEMENT is enabled.
Jira: ZEP-1325
Change-Id: Ic6cd4b8dc0a17c6a413cabf6509b215a4558318d
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
A new shared memory area has been added to the QMSI bootloader in
order to store the GDT in RAM reliably.
Add the new entry to the QUARK D2000 linker script and new
kconfig options:
* CONFIG_BSP_SHARED_GDT_RAM_ADDR to set the address location
of the GDT in RAM.
* CONFIG_BSP_SHARED_GDT_RAM_SIZE to set the size used by the
GDT in RAM.
This is only enabled when CONFIG_SET_GDT is NOT set.
Change-Id: Ie084079475853dce153dd9f3e88ad4a9784bdedf
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
A new shared memory has been added to the QMSI bootloader in order to
store the GDT in RAM reliably.
Add this new entry to the QUARK SE C1000 linker script and new kconfig
options:
* CONFIG_BSP_SHARED_GDT_RAM_ADDR to set the address location
of the GDT in RAM.
* CONFIG_BSP_SHARED_GDT_RAM_SIZE to set the size used by the
GDT in RAM.
Additionally, both BSP_SHARED_RAM_ADDR and BSP_SHARED_RAM_SIZE have been
renamed to BSP_SHARED_RESTORE_INFO_RAM_ADDR and
BSP_SHARED_RESTORE_INFO_SIZE respectively, in order to better resemble
what these options are for. All these configs are available
unconditionally.
Change-Id: I07ee8b440d4a3f5e9bdeb62441ff6a7bd6d4c153
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Bartlomiej Majka <bartlomiejx.majka@intel.com>
For the next QMSI release, the shared restore info address has been
modified to 0xA8013FDC .
Change-Id: I72eaef4f15f7ef6fb8e7eb9acd7d96451623e103
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Update the builtin QMSI code to 1.4 (RC2).
The below shim drivers were updated for API or interface changes:
- aio
- counter
- i2c_ss
- rtc
- wdt.
Also, arch soc specific power management code were updated.
Jira: ZEP-1572
Change-Id: Ibc8fae032a39ffb2c2c997f697835bc0208fd308
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
The entry point specified in the elf file should always point to
executable code, and not to the interrupt vector table. Pointing to the
vector table as the entry point in the elf file presents problems with
running the kernel against a debugger as the debugger starts the program
counter at the top of the interrupt vector table.
Change-Id: I76051f6e99a44bab72936670bead5fb8191a6ec7
Signed-off-by: Tim Nordell <tim.nordell@nimbelink.com>
Rename devices. For example, the two i2c devices in the
quark se sensor sub-system will have name string "I2C_0"
and "I2C_1", while the other two i2c devices accessible to
both x86 and arc will have name string "I2C_2" and "I2C_3".
This is valid only when you build arc binary.
It does not apply if you build x86 or arm binary. Similar change is
also made for GPIO and SPI.
Jira: ZEP-1588 ZEP-1614
Change-Id: Ibad4486e70e0aaf287763514a5a9d28b43bca094
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Added a linker script that shall be common to most riscv SOCs.
Linker script also accounts for execution in place in ROM, when
CONFIG_XIP is set.
Nonetheless, riscv32 SOCs (like pulpino) requiring a different
system layout can still define their own linker script.
Change-Id: I3ad670446d439772c29a8204e307ac79643dc650
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.
The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.
Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This is a zero-copy networking implementation of Ethernet driver.
Limitations:
- one shot PHY setup, no support for PHY disconnect/reconnect
- no support for devices with DCache enabled due to missing
non-cacheable RAM regions in Zephyr.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1492
Change-Id: Ib944f91193efbd12c1142b0bcf1f635388bf1b87
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added basic USART driver for Atmel SAM MCU family. USART is a very
comprehensive module, currently only basic features sufficient to
support printf functionality are implemented by this driver.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ia9710e4069243fb6c30de45953dfc1fe1266b63a
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Added common, internal, always available SAM HAL drivers: pmc, gpio.
Note: these drivers are meant to be used by other SAM drivers, not by
a user space program directly.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: I00cca358f27790dc94cf79f840584b85ff5191f6
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Added support for early SoC configuration which does not belong
conceptually to system initialization. ERASE, JTAG TDI pins are
currently configured here.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Id51adddb4c7cce22907af214461d75db83df129a
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added support for Atmel SAM E70 (Cortex-M7) MCU:
- Kconfig files
- device start-up code
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ide4fd5dadd94897303090a6507b8d048773b645e
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
As cpu_idle.S is the only bit of code that is using the SCB asm defines,
so to allow us to remove scb.h in the future lets move the defines that
are used just into cpu_idle.S
Jira: ZEP-1568
Change-Id: I3c3a6f145ec4c1a43f076d079d5fe1694c255b78
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
A number of SoCs clear out the Mem/Bus/Usage and Hard Fault exceptions
during init. Lets refactor that into a common function so we don't have
to keep duplicating it over and over.
Change-Id: Ida908a9092db37447abcf3c9872f36937982f729
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch fixes the UART4 base address on the ARM MPS2 platform.
Change-Id: I14bf2a4dc2378d4b2c4295a75cd68c6c895fbd60
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Kill of nvic.h and use either CMSIS helper functions for NVIC or direct
NVIC register access via CMSIS for IRQ handling code.
Jira: ZEP-1568
Change-Id: If21910b9293121efe85c3c9076a1c2b475ef91ef
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace _ScbExcPrioSet with calls to NVIC_SetPriority as it handles both
interrupt and exception priorities. We don't need to shift around the
priority values for NVIC_SetPriority.
Jira: ZEP-1568
Change-Id: Iccd68733c3f7faa82b7ccb17200eef328090b6da
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds the configuration parametes required to enable CMSDK
(Cortex-M System Design Kit) Drivers at MPS2 soc level.
It provides as well the definitions for the MPS2 System Control
registers.
Change-Id: I06181dcfeb4fb887425b85ec9a99c268c857a34e
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Adds initial support for the kw41z SoC. This is the first SoC in the
Kinetis W (wireless connectivity) series added to Zephyr. The kw41z
integrates a 2.4 GHz radio transceiver, BLE link layer hardware, and an
802.15.4 packet processor with an ARM Cortex M0+. It has 512 KB flash,
128 KB SRAM, and can run the system clock at up to 48 MHz.
This SoC currently has mcux shim drivers for lpuart (serial), gpio,
pinmux, i2c, and flash.
Jira: ZEP-1389
Change-Id: I8cff6d203867ba3ace7e05c36441dc8f3cbca8d8
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Renames the flash security section so it makes sense for other Kinetis
devices, not just k64. In Kinetis reference manuals, this section is
referred to as the 'flash configuration field'.
Change-Id: I2b7c7cc1ec2541419d77878d367d96c9ceb7a0cf
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux lpuart driver to adapt it to the Zephyr
serial interface.
NXP has multiple uart hardware blocks that implement different features
and have different register maps. The k64 has a uart block called
'uart', while the kw41 has a uart block called 'lpuart' (low power
uart). The MCUXpresso SDK provides separate drivers for each type of
uart block but with similar software interfaces. As a result, there are
also separate shim drivers in Zephyr. There is a 1:1:1 relationship
between hardware block, mcux driver, and mcux shim driver.
Because we now have two mcux shim drivers for the uart interface, a new
naming convention is created:
<interface>_mcux_<hw block>
Where <interface> is the name of the Zephyr interface, in this case
'uart'. This convention is not new.
<hw block> is the name of the NXP hardware block, in this case 'lpuart'.
This is the new part, and distinguishes different hardware blocks
for the same interface.
Change-Id: I3a80b9bffa116bbb2b02ee950d4bdd79a19a4edc
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Nordic Semiconductor's Software Development Kit's HAL layer
provides a set of low-level header and sourcefiles that give access
to the different hardware peripherals of Nordic ICs.
This patch includes the new files in the build and refactors the Kconfig
and Kbuild files in ext/hal/nordic to acommodate for the presence of the
new HAL layer.
Change-Id: Ie8e1a4c9fcc7e9058a9d16a2692ef1789603aa53
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The STM32 GPIO driver extended the generic GPIO driver interace with
the concept of OPEN_DRAIN. There is previous discussion about
representing such concepts in the GPIO interface in a more general
fashion here:
https://lists.zephyrproject.org/archives/list/devel@lists.zephyrproject.org/thread/6DCFUAKCOOOBHUO3ZK45ES6IQXOEOFWN/
The DRIVE STRENGTH interface supports the concepts of OPEN DRAIN and
other variants supports by other vendors hardware.
Adjust the STM32 GPIO driver to use the DRIVE STRENGTH interface. A
following patch will address the simplication of gpio.h
Change-Id: I56b0792ec2b21f1adc673dff019288dc8573d005
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This patch changes Quark SE power drivers to support multicore scenarios
e.g. both LMT and ARC core are enabled and manage power.
Handling LPS states in multicore scenarios are dead simple because LPS
states are core-specific states. It means that putting the LMT core in
LPS doesn't affect the ARC core, and vice-versa. DEEP_SLEEP state, on
the other hand, affects both cores since it turns power off from the SoC
and both cores are shutdown. It means that if LMT puts the system in
DEEP_SLEEP, ARC core is shutdown even if it is busy handling some task.
In order to support the multicore scenario, this patch introduces the
SYS_POWER_STATE_DEEP_SLEEP_2 state to both ARC and x86 power drivers.
On ARC, this state works as following:
1) Save ARC execution context;
2) Raise a flag to inform the x86 core that ARC is ready to enter in
DEEP_SLEEP;
3) Enter in the lowest core-specific power state, which in this case is
LPSS.
On x86, DEEP_SLEEP_2 is very similar to DEEP_SLEEP. The difference relies
in the post_ops() which calls _arc_init() in order to start ARC core so
it can restore its context.
This patch also adds the test/power/multicore/ directory which provides
sample application to x86 and ARC cores in order to easily verify the
multicore support. In test/power/multicore/README.rst you can find more
details regarding the applications.
Jira: ZEP-1103
Change-Id: Ie28ba6d193ea0e58fca69d38f8d3c38ca259a9ef
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This avoids asm files from having to explicitly define the _ASMLANGUAGE
symbol themselves.
Change-Id: I71f5a169f75d7443a58a0365a41c55b20dae3029
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
The K_<thread option> flags/options avaialble to users were hidden in
the kernel private header files: move them to include/kernel.h to
publicize them.
Also, to avoid any future confusion, rename the k_thread.execution_flags
field to user_options.
Change-Id: I65a6fd5e9e78d4ccf783f3304b607a1e6956aeac
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
They are internal states, not user-facing.
Also prepend an underscore since they are kernel internal symbols.
Change-Id: I53740e0d04a796ba1ccc409b5809438cdb189332
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
They are not part of the API, so rename from K_<state> to
_THREAD_<state>.
Change-Id: Iaebb7d3083b80b9769bee5616e0f96ed2abc5c56
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Replace _scs_relocate_vector_table with direct CMSIS register access and
use of __ISB/__DSB routinues. We also cleanup the code a little bit to
just have one implentation of relocate_vector_table() on ARMv7-M.
Jira: ZEP-1568
Change-Id: I088c30e680a7ba198c1527a5822114b70f10c510
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CMSIS provides a complete implentation for reboot, we can utilize it
directly and reduce zephyr specific code.
Jira: ZEP-1568
Change-Id: Ia9d1abd5c1e02e724423b94867ea452bc806ef79
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As a first step towards removing the custom ARM Cortex-M Core code
present in Zephyr in benefit of using CMSIS, this change replaces
the use of the custom core code with CMSIS macros in
enable_floating_point().
Jira: ZEP-1568
Change-id: I544a712bf169358c826a3b2acd032c6b30b2801b
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Support using CMSIS defines and functions, we either pull the expect
defines/enum from the SoC HAL layers via <soc.h> for the SoC or we
provide a default set based on __NVIC_PRIO_BITS is defined.
We provide defaults in the case for:
IRQn_Type enum
*_REV define (set to 0)
__MPU_PRESENT define (set to 0 - no MPU)
__NVIC_PRIO_BITS define (set to CONFIG_NUM_IRQ_PRIO_BITS)
__Vendor_SysTickConfig (set to 0 - standard SysTick)
Jira: ZEP-1568
Change-Id: Ibc203de79f4697b14849b69c0e8c5c43677b5c6e
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In preperation for removing the scb/scs layers and using CMSIS directly
lets remove all the _Scb* and _Scs* functions that are not currently
used.
Jira: ZEP-1568
Change-Id: If4641fb9a6de616b4b8793d4678aaaed48e794bc
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
ARM's Cortex-M Prototyping System (or MPS2) [1] is a board containing
devices such as RAM, ethernet and display, and at its heart there is an
FPGA which can be programmed with various 'SoCs' which implement the
CPU, SRAM, UARTs, SPI, DMA, etc. There are also software simulations of
systems based on this hardware which are part of ARM's Fixed Virtual
Platforms (FVPs).
All of the above could be regarded SoCs in the same series so we will
treat them as such in Zephyr.
In this initial patch we add SoC support for the public FPGA image
which implements a Cortex-M3 CPU, and includes definitions to support
use of the UARTs on this.
ARM's documentation for MPS2 images are titled 'Application Note ANnnn'
where the number nnn is different for each 'SoC'. E.g. Application Note
AN385 is for "ARM Cortex-M3 SMM on V2M-MPS2" [2]. The files ARM supply
for programming the board firmware also make extensive use of the ANnnn
nomenclature, so we will use this for the SoC name in Zephyr. E.g. the
Cortex-M3 SoC will be called 'mps2_an385'. Note, it is not possible to
use the CPU type (e.g. M3) for the name as there are multiple FPGA
images for some CPU types (e.g. there are three Cortex M7 images
with differing FPU and MPU support).
[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0385c/index.html
Change-Id: Ice54f2d2cde7669582337f256c878526139daedd
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Now that we have a more generic mcux spi driver that can be used across
multiple Kinetis SoCs, remove the specific k64 spi driver.
Jira: ZEP-1374
Change-Id: Ifc324374f305837f5e3d2cfd7ad30d3608865b5b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch adds the timers IRQ map to the ARM Beetle SoC platform.
Jira: ZEP-1300
Change-Id: If38a197210f71ae90c7ee6274395f064116faf72
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
On other targets, CONFIG_TEXT_SECTION_OFFSET allows the entire image to
be moved in memory to allow space for some type of header. The Mynewt
project bootloader prepends a small header, and this config needs to be
supported for this to work.
The specific alignment requirements of the vector table are chip
specific, and generally will be a power of two larger than the size of
the vector table.
Change-Id: I631a42ff64fb8ab86bd177659f2eac5208527653
Signed-off-by: David Brown <david.brown@linaro.org>
Now that we have a more generic mcux serial driver, remove the uart_k20
driver.
Jira: ZEP-719
Change-Id: I51a3237454140feabbfe18ac2c8ee451e572c7be
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Stop using the specific uart_k20 driver by default and start using the
more generic mcux uart driver instead.
Jira: ZEP-719
Change-Id: I7b107ea7118887591362159283ebb5413b45595a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Implementation includes adding some defines in the pinmux,
adjusting gpio driver to specific defines for STM32F3X family,
adding specific functionality in the F3X SoC definition.
Change-Id: I465c66eb93e7afb43166c4585c852e284b0d6e67
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
SOC_FLASH_NRF5 is compatible with any nrf5 device, so enable the driver
by default if CONFIG_FLASH is also enabled.
Change-Id: I6ddf7cc41bb28071f682e78661b184a8e2ee7aa9
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
It is called before early SoC initialization, so remove the duplicated
code from other boards and just set it by default when using XIP.
This can later be used when adding bootloader support, as an
additional option could be created to move the VTOR offset to a
different address.
Change-Id: Ia1f5d9a066de61858ee287215cefdd58596b6b1c
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
pulpino soc has custom-extended riscv ISA that is accounted
for if CONFIG_RISCV_GENERIC_TOOLCHAIN is not set.
(ex: bit manipulation asm opcodes)
Change-Id: I4dafc4ebc2fedcc4eb6a3dedd0412816afea6004
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Force-align all variables defined via asm .word to ensure 4-byte
alignment.
The straddled_tick_on_idle_enter variable was a bool, which resolved in
an one-byte quantity. Changing it to a 32-bit integer. It would have
occupied 4 bytes anyway with alignment.
Fixes ZEP-1549.
Change-Id: If5e0aa1a75dbc73d896b44616f059d221fe191c6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The mcux pinmux driver enables the port clocks, so the soc init no
longer needs to enable them. Also removes some soc defines that were
used only by the legacy k64 pinmux driver.
Change-Id: I63174bef4024b5a09a73f941cea0aec691c759d3
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Now that we have a more generic mcux gpio driver that can be used across
multiple Kinetis SoCs, remove the specific k64 gpio driver.
Jira: ZEP-1394
Change-Id: I177f96a75e441b70c523e74e99f1b7a54eac6b0e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Stop using the specific k64 gpio driver by default and start using the
more generic mcux gpio driver instead.
Jira: ZEP-1394
Change-Id: I54ec9b62cc8790b8973efc34fa36d17da523971e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Moves the uart console pins from the k64 soc init to the frdm_k64f and
hexiwear_k64 board pinmux tables. Not having these pins in the board
pinmux tables led one to believe that no pins in PORTB were being used
on the hexiwear_k64 board, and thus the port was incorrectly disabled by
default.
Also fixes PORTB to be enabled by default if the uart console is used.
Change-Id: Ide6b7b34dfba8a75a02a8f2bf37cce843afb92f1
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch provides initial support for the SoC STM32F107. This SoC
belongs to the Connectivity Line devices.
Connectivity line family incorporates up to 14 communication
interfaces such as: 2 x I2C, 5 x USART, 3 x SPI, 2 x CAN, USB 2.0,
10/100 Ethernet MAC.
Change-Id: I5cb2c458bce9ec1558b4168e87a7003ad9f606a5
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that all the ksdk/mcux shim drivers use the config HAS_MCUX, we can
remove the config HAS_KSDK.
Change-Id: I94b7db41efae10c9234681aeb57f94e67a33c262
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Renames the ksdk random generator shim driver to mcux.
Change-Id: I8bc376937fed3024c809782139a0a72c7332f89a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The ksdk pinmux dev driver was previously merged into the regular ksdk
pinmux driver, and the config PINMUX_DEV_KSDK was removed. Two
references were inadvertantly left behind, so remove them now.
Change-Id: I77394be5459d55a9f16e7bd2b3c9d688c4605b4f
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
stm32f411re SoC could run at system clock above 84MHz.
This was not taken into account in __setup_flash function which configure
flash latency depending on system clock. This is now corrected.
Assert added to ease error detection.
Change-Id: I49b92256d611ef464171fb1d8812a4c4d3c27ab8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Previously, CC3200 drivers had two options to use the peripheral
driver library APIs:
1) Build driverlib SDK files in Zephyr, in ext/hal/ti/cc3200/*
2) Link directly with the driverlib.a, from an externally installed
TI CC3200 SDK.
A new option is added to replace option 2), and is now the default:
3) Use the driverlib functions already provided in ROM.
This enables a savings in code size, which will depend on the
types of device drivers configured and the number of SDK
APIs actually used.
A rom_report build of the shell sample application showed
a savings of about 2kb in code space using this new config option.
Change-Id: Ie1ede6f7aacd23db20f5292e776f1dfeab5c7fe0
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The cortex-m7 is an implementation of armv7-m. Adjust the Kconfig
support for cortex-m7 to reflect this and drop the unnecessary,
explicit, conditional compilation.
Change-Id: I6ec20e69c8c83c5a80b1f714506f7f9e295b15d5
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Precursor patches have arranged that conditional compilation hanging
on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the
config variable to reflect this.
Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Precursor patches have arranged all conditional compilation hanging on
CONFIG_CPU_CORTEX_M0_M0PLUS such that it actually represents support
for ARM ARMv6-M, rename the config variable to reflect this.
Change-Id: I553fcf3e606b350a9e823df31bac96636be1504f
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The ARM code base provides for three mutually exclusive ARM
architecture related conditional compilation choices. M0_M0PLUS,
M3_M4 and M7. Throughout the code base we have conditional
compilation gated around these three choices. Adjust the form of this
conditional compilation to adopt a uniform structure. The uniform
structure always selects code based on the definition of an
appropriate config option rather the the absence of a definition.
Removing the extensive use of #else ensures that when support for
other ARM architecture versions is added we get hard compilation
failures rather than attempting to compile inappropriate code for the
added architecture with unexpected runtime consequences.
Adopting this uniform structure makes it straight forward to replace
the adhoc CPU_CORTEX_M3_M4 and CPU_CORTEX_M0_M0PLUS configuration
variables with ones that directly represent the actual underlying ARM
architectures we provide support for. This change also paves the way
for folding adhoc conditional compilation related to CPU_CORTEX_M7
directly in support for ARMv7-M.
This change is mechanical in nature involving two transforms:
1)
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
is transformed to:
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
...
2)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
#else
...
#endif
is transformed to:
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
...
#else
#error Unknown ARM architecture
#endif
Change-Id: I7229029b174da3a8b3c6fb2eec63d776f1d11e24
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Adjust the layout of various ARM assember files to conform to the norm
used in the majority of files.
Change-Id: Ia5007628be5ad36ef587946861c6ea90a8062585
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
I've moved the call for icache_setup from nanoArchInit() to
_PrepC(), because there is a lot of code executed now before
nanoArchInit() is called, and all this time the i-cache would
be off. It should be turned on as early as possible to make
initialization faster.
Change-Id: I76a809d57a1bf9aacf51e7bb9fe8c8425f37aa13
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The 16k RAM nRF51 variants pose a challenge to get applications to fit
within the available memory. Make the default ISR stack size smaller
than the previous 2k default, but big enough to run fully functional
Bluetooth controller and host stacks.
Change-Id: Ie7c5bb21a3ba620d283e6228a2482d280f85119d
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
On the nRF5x platforms we need always need the NRF_RTC_TIMER and it
depends on the CLOCK_CONTROL_NRF5. So enable all of these always.
Fixes issues if one tries to build nRF5x platforms w/o CONFIG_BLUETOOTH.
Change-Id: I0f9af785e785f37ec289a935ddf70ee6dec08cd4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
These two fields in the thread structure control the preemptibility of a
thread.
sched_locked is decremented when the scheduler gets locked, which means
that the scheduler is locked for values 0xff to 0x01, since it can be
locked recursively. A thread is coop if its priority is negative, thus
if the prio field value is 0x80 to 0xff when looked at as an unsigned
value.
By putting them end-to-end, this means that a thread is non-preemptible
if the bundled value is greater than or equal to 0x0080. This is the
only thing the interrupt exit code has to check to decide to try a
reschedule or not.
Change-Id: I902d36c14859d0d7a951a6aa1bea164613821aca
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Some thread fields were 32-bit wide, when they are not even close to
using that full range of values. They are instead changed to 8-bit fields.
- prio can fit in one byte, limiting the priorities range to -128 to 127
- recursive scheduler locking can be limited to 255; a rollover results
most probably from a logic error
- flags are split into execution flags and thread states; 8 bits is
enough for each of them currently, with at worst two states and four
flags to spare (on x86, on other archs, there are six flags to spare)
Doing this saves 8 bytes per stack. It also sets up an incoming
enhancement when checking if the current thread is preemptible on
interrupt exit.
Change-Id: Ieb5321a5b99f99173b0605dd4a193c3bc7ddabf4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Use least significant bits for common flags and high bits for
arch-specific ones.
Change-Id: I982719de4a24d3588c19a0d30bbe7a27d9a99f13
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This will allow for an enhancement when checking if the thread is
preemptible when exiting an interrupt.
Change-Id: If93ccd1916eacb5e02a4d15b259fb74f9800d6f4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
GCC 6.x for ARC does not recognize the options
-mARCv2EM and -mav2em anymore.
Both options replaced in Makefile by -mcpu=quarkse_em.
Change-Id: I9dec26dd64b4738976704a39455fe4241406db9e
Signed-off-by: Juro Bystricky <juro.bystricky@intel.com>
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
GCC 6.x for ARC does not recognize the options
-mARCv2EM and -mav2em anymore.
Both options replaced in Makefile by -mcpu=arcem.
Change-Id: Ic86bf51cd5fb1a67ba2cd75998cd907e26996347
Signed-off-by: Juro Bystricky <juro.bystricky@intel.com>
This option has side effects. It also tells the compiler not to generate
these checks in the first place. The checks call abort() which doesn't
exist in our environment.
This patch gets rid of linker errors due to missing abort() in the 0.9 SDK.
Change-Id: Ibc5aeb5458d0bded714c9c074cdf08112733428b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set have a reduced set of registers and fields compared to
the ARMv7-M compliant processors.
This change goes through all core registers and disables or removes
everything that is not part of the ARMv6-M architecture when compiling
for Cortex-M0.
Jira: ZEP-1497
Change-id: I13e2637bb730e69d02f2a5ee687038dc69ad28a8
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.
Keep the legacy samples/tests as is.
Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable arc to access the i2c controller on I/O fabric.
There are two i2c controllers on quark se SoC. One is attached
to the I/O fabric and the other one is in the sensor system.
X86 cpu is only able to access the i2c controller on the I/O
fabric and the access is supported by existing code. HW allows
arc to access both controllers. But, the existing code only
gives arc access to the controller in the sensor sub-system.
Let's grant arc the access to the controller on I/O fabric as
well by the following changes.
1. Add i2c_qmsi.c into arc compilation.
2. Use the already defined macros to choose interrupt numbers
and do interrupt unmasking automatically based on the
compilation targets.
3. Add new symbols in Kconfig including driver names for both
controllers
Jira: ZEP-1189
Change-Id: I317da6038c50e0c8bd16f446182c1f8bdf6d3ba2
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Enable arc to access the spi controller on I/O fabric.
There are two spi controllers on quark se SoC. One is attached
to the I/O fabric and the other one is in the sensor system.
X86 cpu is only able to access the spi controller on the I/O
fabric and the access is supported by existing code. HW allows
arc to access both controllers. But, the existing code only
gives arc access to the controller in the sensor sub-system.
Let's grant arc the access to the controller on I/O fabric as
well by the following changes.
1. Add spi_qmsi.c into arc compilation.
2. Use the already defined macros to choose interrupt numbers
and do interrupt unmasking automatically based on the
compilation targets.
3. Add new symbols in Kconfig including driver names for both
controllers
Jira: ZEP-1190
Change-Id: I40a5d423d4b7986a897834d1a3831938005eda6f
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
HW allows both arc and x86 to access the pwm attached to the
quark soc I/O fabric. The existing code only allows x86 to
do this. Let's give arc the access.
Change-Id: Ie88649fea41bf86b84876c260f97dd4c12fd0b81
Signed-off-by: Baohong liu <baohong.liu@intel.com>
Obsolete, replaced by _set_thread_return_value().
Change-Id: I23e9cfc07e43542f0965817edc3552d456fd2ef3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
