NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
STM32H753xx is similar to STM32H743xx except that it has crypto/hash
hardware acceleration and the memory configuration is always 2Mbytes
flash and 1Mbyte RAM.
Signed-off-by: Petri Oksanen <petri@iote.ai>
Include generic header stm32_ll_hsem.h from stm_hsem.h (which is used
by multiple drivers) instead of depending on soc.h.
Signed-off-by: Martin Jäger <martin@libre.solar>
SOF uses different SSP clock rates on different cAVS versions. Frequency
tables are provided in platform_ssp_freq[] arrays in clk.c for each
version and the default entry is selected by the SSP_DEFAULT_IDX index.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The current SAM4S define at board level common flags that should be on
soc defines. Add common flags at SoC Kconfig defines and drop the
correspondent at board defines.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current SAM4E define at board level common flags that should be on
soc defines. Add common flags at SoC Kconfig defines and drop the
correspondent at board defines.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add separated Kconfig file for Bluetooth 5.1 Direction Finding.
Enable controller support for:
- transmission of CTE
- 2us antenna switching
- 1us antenna switching
if build for nRF52833 SOC.
Add HAS_HW_NRF_RADIO_BLE_DF to nrf52833 SOC configuration.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.
STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...
The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.
Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Configures i.MX RT SoCs that support cacheable external SDRAM to use the
DTCM linker section for Segger RTT and SystemView data.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The SAM4L have a unique I2C driver. It shares simultaneously pins for
both master and slave controllers. Each controller have their own
instance. This introduces the TWIM controller that handles only the
master part.
The TWIM controller uses no copy and the driver was prepared to work
with both 7 and 10 bits address. The controller can handler up to 256
bytes for a single transfer allowing long data communication with
almost no CPU intervention.
The driver was wrote specifically to Zephyr. It receives a transfer
list of from upper layers to a specific device on the bus. It programs
the first and second transfer, if it exists, before start. At end of
full read/write interrupt, will program the next data block. This
process repeats until all transfers be executed. The driver uses
interrupt from TWIM to check for erros or program next tranfer.
Future work can enable low power mode on the driver allowing long
transfers with low power consumption.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add i2c1 interface for stm32l552xx and stm32l562xx microcontrollers
and enable i2c1 that connects to lsm6dso sensor module on the
stm32l562e_dk board.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
This commit implements the architecture specific parts for the
Zephyr tracing subsystem on SPARC and LEON3. It does so by calling
sys_trace_isr_enter(), sys_trace_isr_exit() and sys_trace_idle().
The logic for the ISR tracing is:
1. switch to interrupt stack
2. *call sys_trace_isr_enter()* if CONFIG_TRACING_ISR
3. call the interrupt handler
4. *call sys_trace_isr_exit()* if CONFIG_TRACING_ISR
5. switch back to thread stack
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This section was being put in the wrong region, and was in L1-cached
incoherent memory. That's wrong, as users are expected to expressly
ask for "__incoherent" memory and do manual cache management if
required. Default memory of all types should be uncached and
coherent.
Very few spots use this and cache effects tend to be ephemeral, so it
was somewhat obscure. It was discovered via an SMP race when using
logging very close to system start where the log thread on the second
CPU will race with messages added on the first -- log messages are
stored in a __noinit mem_slab.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This platform had separate backends for the log subsystem and printk
handler, which was silly. Unify them to use the same backend so they
don't clobber each other.
This patch appears to be a lot of lines, but it's really mostly code
motion and renaming.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Change adds missing TX power dependencies. nRF52833 and nRF52820 SoCs
also support higher TX power values.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
1. Code for the power mananagement is available
in source format
2. Increase the core speed to 250MHz.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
These MCUs have 32Kbytes of Flash and 8Kbytes of RAM. They are still
able to run a number of samples.
Signed-off-by: Steven Daglish <s.c.daglish@gmail.com>
In CMakeLists.txt, the MEC1501 specific timing functions are
only compiled if CONFIG_CORTEX_M_DWT=n. However, in SoC's
kconfig, CONFIG_SOC_HAS_TIMING_FUNCTIONS is defaulted to y
unconditionally. This results in the timing subsys looking
for SoC-based timing functions but those are not compiled.
So add a condition to kconfig similar to CMakeLists.txt where
SoC timing functions are only enabled when CONFIG_CORTEX_M_DWT=n.
Fixes#29969
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a Kconfig option (enabled by default) the enables the low-frequency
oscillator (LFXO) functionality on the XL1 and XL2 pins in the nRF53
SoC initialization routine. This cannot be done in the clock control
driver, as it was done so far, because that won't work in a setup where
the application core image does not use the system clock at all.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Replace direct register accesses in the SoC initialization routine
with proper calls to nrfx HAL functions.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
We should not be initializing/starting/stoping timing functions
multiple times. So this changes how the timing functions are
structured to allow only one initialization, only start when
stopped, and only stop when started.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The nRF5340 (P)DK is equipped with the MX25R64 flash memory. Add a dts
node for that chip in the board definition as well as the missing QSPI
node in the nRF5340 SoC definition.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The IRQ handler has had a major changes to manage syscall, reschedule
and interrupt from user thread and stack guard.
Add userspace support:
- Use a global variable to know if the current execution is user or
machine. The location of this variable is read only for all user
thread and read/write for kernel thread.
- Memory shared is supported.
- Use dynamic allocation to optimize PMP slot usage. If the area size
is a power of 2, only one PMP slot is used, else 2 are used.
Add stack guard support:
- Use MPRV bit to force PMP rules to machine mode execution.
- IRQ stack have a locked stack guard to avoid re-write PMP
configuration registers for each interruption and then win some
cycle.
- The IRQ stack is used as "temporary" stack at the beginning of IRQ
handler to save current ESF. That avoid to trigger write fault on
thread stack during store ESF which that call IRQ handler to
infinity.
- A stack guard is also setup for privileged stack of a user thread.
Thread:
- A PMP setup is specific to each thread. PMP setup are saved in each
thread structure to improve reschedule performance.
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Nicolas Royer <nroyer@baylibre.com>
