Adds channel 15 to the pool of grtc channels available
for allocation (i.e. with 'z_nrf_grtc_timer_chan_alloc')
on nRF54H20.
The change is motivated by lack of available channels
for the nrf_802154_timestamper when building for nRF54H20.
Signed-off-by: Piotr Koziar <piotr.koziar@nordicsemi.no>
This commit should address the #73803 issue
where the DMA node does not provide support
for the #dma-cells binding. Peripherals should
specify one or more DMA channels via the dmas
and optionally dma-names DT properties.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Declare power state constraints for a device in devicetree.
It allows a map between device instances and power states that disable
their power. This information is used by a new API
(pm_policy_device_power_lock_put/get) that automically set/release
pm state constraints.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
adsp_memory.h is pretty much the same for all ace platforms.
Generalize it getting register address from devicetree and
and move it to a common place.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Support NXP ENET_1G on mimxrt1170_evk/mimxrt1176/cm7 platform.
Added test configuration sample.net.zperf.nxp_enet1g and
documented the usage of the ethernet driver with ENET_1G
peripheral.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add driver for Realtek RTL8211F 10/100/1000M ethernet PHY.
This driver implements vendor specific behaviour like
detecting link state change by GPIO interrupt, which is not
present in the generic MII driver.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
- Added nxp,enet1g compatible to distinguish between ENET (nxp,enet)
and ENET_1G (nxp,enet1g) peripherals within the same driver.
- Added config ETH_NXP_ENET_1G to enable 1G mode of operation on ENET_1G.
- Support RGMII mode of connection between MDIO and PHY to be
able to work with ENET_1G peripheral and support 1000M speed.
- Removed performing of PHY reset before configuring link - it is
not desirable for RTL8211F PHY connected to ENET_1G on RT1170.
Reset of other PHYs can be performed by PHY driver itself if required.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add option for RGMII connection type between the MAC and the PHY
device into the ethernet controller binding.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Introduce driver for ov7670 camera, supporting QCIF,QVGA,CIF, and VGA
resolution in YUV and RGB mode.
Support was verified on the FRDM-MCXN947, using the SmartDMA camera
engine, which is enabled in the following PR:
https://github.com/zephyrproject-rtos/zephyr/pull/72827
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The byteSENSI-L is a fun LoRa device based on nRF52 MCU that integrates
many sensors.
Signed-off-by: Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Guy Morand <guy.morand@bytesatwork.ch>
Configure the quad-spi in DualFlash Mode
This property of the stm32 boards will access simultaneously
two identical quad-flash external memories connected to
2 quad-spi banks (pins).
Dual Flash Mode is possible on stm32 series with QUADSPI_CR_DFM
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add devicetree nodes for the two FlexCAN instances present on the
MCXN94x. Only CAN classic is enabled for now due to issues with FlexCAN FD
in relation to the implementation on this SoC.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add devicetree nodes for the Reset Information registers on nRF54H20,
along with a new binding.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Introduce the stm32h7RS serie to the clock_controller,
based on the stm32h7 clock driver
Datasheet DS14359 rev 1 gives CPU max freq of 500MHz
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the new stm32h7rs serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce the stm32h7RS serie to the clock rcc controller,
and the exti interrupt controller based on the stm32h7 rcc bindings.
Three PLL clocks are available.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
low level 1b: 4mA or 2mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for configuration of the ARM PLL on the iMXRT1170/1160
series SOCs. This PLL is used to generate the M7 core frequency, and is
an integer pll. Provide default configurations for the RT1160 and RT1170
targeting 600MHz and 1GHz respectively.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add bindings for nxp display interfaces. These bindings describe the 6
and 40 pin FPC connectors used for displays on several NXP EVKs using
gpio nexus nodes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add devicetree node of stm32 PWR peripheral that controlls wake-up pins.
The new node includes child nodes for wake-up pins configuration.
We only add these nodes for STM32 SoC series that support Poweroff.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add DT binding for stm32 PWR peripheral that controlls wake-up pins.
This binding primarily introduces wake-up pins configuration in
a unifed way that takes into consideration the variations between
STM32 SoC series & facilitates the association of GPIO pins with
their corresponding wake-up pins.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Deprecate the CAN controller bus-speed/bus-speed-data properties and rename
them to bitrate/bitrate-data to match the terminology used in other CAN
devicetree properties and the CAN subsystem API.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Make it possible to disble device power management individually per
power state. This allows targets tuning which states should
(and which should not) trigger device power management.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
I chose this approach instead of software rotation because I need it for
an ultra low power project.
Rotation in steps of 0, 90, 180, 270 degrees is done by changing
the data entry modes.
This commit removes the orientation-flipped property as it is redundant.
I made the assumption that the current driver implementation is right
about controller X/Y versus display width/height. The display controller X
parameter matches with the display height (dts) and display controller Y
parameter matches with the display width (dts). It looks like display
manufacturers choose to have it like this because a wider screen probably
makes more sense.
Tested on the reel_board with a 250x122 display (ssd1673 controller)
and a custom PCB with a 200x200 display (ssd1681 controller).
Also tested all orientations with various width/height dts overrides.
Signed-off-by: Sven Depoorter <svndepoorter@gmail.com>
- The MK22FN512VLH12 chip, installed on frdm_k22f,
has 512 KB of Program Flash and 128KB SRAM
according to the K22P121M120SF7RM.pdf manual (page 55).
- Fix the flash size to 512KB (was 1MB).
- Add nxp_k22fn512.dtsi with correct flash size value.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add a digi_dietemp node for the STM32 Digital Temperature Sensor into
stm32h723.dtsi (used as a base for H723, H725, H730 and H735) and
stm32h7a3.dtsi (used as a base for H7A3, H7B0 and H7B3).
The sensor is not available on other H7 SoCs.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This add basic support for the STM32 Digital Temperature Sensor found
notably on the STM32H7 series. It work in interrupt mode and support
basic power device management.
It does not support the more advanced features like using the
temperature threshold, triggers from LPTIM or using the LSE clock in
during sleep or stop.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Improve the binding descriptions for the atmel,at24 and atmel,at25 EEPROM
compatibles. These compatibles work for a number of different EEPROM
families manufactured by vendors other than Atmel.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit refactors the Intel SSP DAI driver to support dynamic
management of SSP IP. This change additionally separates the
management of the DAI part from the management part of the SSP IP.
Key changes:
- Add new static functions to manage SSP IP power.
- Update the DAI SSP configuration functions to use the new management
approach.
- Update device tree bindings and instances to reflect the new SSP IP
management mechanism.
- ace30 (PTL) support.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit adds definition of ACE 3.0 Panther Lake board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
