Commit Graph

238 Commits

Author SHA1 Message Date
Christian Taedcke
1897dcf86e dts: arm: nxp: nxp_lpc55s6x: Fix a few reg sizes
These were found while reviewing the device tree and register addresses.
They are now the same as for the LPC55S28.

Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
2020-12-03 03:58:58 -06:00
Christian Taedcke
67f4d9ff9a dts: arm: nxp: nxp_lpc55s6x: Remove wrong comment
sram4 is not connected to USB. The following sram area that is not part
of the device tree is. So the comment is removed with this commit.

Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
2020-12-03 03:58:58 -06:00
Henrik Brix Andersen
e78421515c dts: arm: nxp: kw40z: remove zephyr,flash-controller chosen node
Remove the zephyr,flash-controller chosen node from the NXP KW40Z SoC
series devicetree. The MCUX SDK version for this SoC is too old to work
with the Zephyr MCUX flash driver shim.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-12-02 23:20:32 -05:00
Maureen Helm
370d02743a dts: arm: Remove peripheral aliases from NXP SoCs
Removes peripheral aliases from all NXP SoCs (Kinetis, LPC, and i.MX),
which are no longer being used after converting their associated drivers
to use DT_INST macros. The watchdog alias remains because it is used by
tests/drivers/watchdog/wdt_basic_api/

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-11-17 11:31:47 -06:00
Maureen Helm
3498d43784 drivers: ethernet: Rework mcux driver to use DT_INST_FOREACH
Reworks the mcux ethernet driver to use DT_INST_FOREACH_STATUS_OKAY and
eliminate a lot of duplicate code between instance 0 and instance 1.

Renames the ERR_MISC interrupt to ERR due to an issue with the
underscore in the device tree preprocessor macros.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-11-03 11:05:55 +01:00
Maureen Helm
25ddc4e0f5 dts: arm: Use DT_SIZE macros for nxp internal memories
Refactors nxp i.mx, kinetis, and lpc soc-level device trees to use
DT_SIZE_K and DT_SIZE_M macros to define internal memory sizes. This is
self documenting and easier to read.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-10-28 11:13:07 -05:00
Crist Xu
237b34ef2d watchdog: Add watchdog driver
Add watchdog driver for the RT1050/60

Signed-off-by: Crist Xu <crist.xu@nxp.com>
2020-10-23 12:52:13 +02:00
Mahesh Mahadevan
2526ca1a4d dts: Add DMA for LPC55S6X
Enable DMA0 and DMA1 for LPC55S6X

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-10-21 06:26:40 -05:00
Mahesh Mahadevan
451e7b862a dts: Update NXP LPC DMA configuration to get channel number
The DMA channel number used for the DMA transfer can now
be specified from the device tree config files

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-10-21 06:26:40 -05:00
Mahesh Mahadevan
c2a40a8c66 dts: Clock control for RT600, LPC54xxx, LPC55xxx
Use the clock control driver to get flexcomm clock
frequency

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-10-15 11:17:24 -05:00
Maureen Helm
f8924af3ce dts: arm: Fix k6x ethernet base address
Commit ac31c4e458 updated the mcux
ethernet driver to get the ethernet peripheral base address from device
tree instead of an nxp hal preprocessor macro. This exposed an error in
the k6x device tree and caused a runtime assertion in networking
applications on the frdm_k64f board:

ASSERTION FAIL [instance < (sizeof(s_enetBases) / sizeof((s_enetBases)[0]))] @ WEST_TOPDIR/modules/hal/nxp/mcux/drivers/kinetis/fsl_enet.c:323

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-10-14 07:05:21 -05:00
Toby Firth
dc37f988e0 drivers: adc: added support adc driver for lpcexpresso55s69
Added shim driver for the LPADC for lpcexpresso55s69 board.

Fixes #22703.

Signed-off-by: Toby Firth <tobyjfirth@gmail.com>
2020-10-12 14:59:40 -05:00
Rick Talbott
60e5e79ca1 drivers: mcux: imx rt flexcan support
Adds imx rt support.
Allows n-number of can interfaces based on device-tree.
Adds a "common" irq name.
Added CAN bus pins and dts for 1060 and 1064 EVK.

Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
2020-09-29 14:03:10 -05:00
Hake Huang
f0f95b16dd board: update rt6xx series sram mapping
update rt6xx series sram mapping to skip 0x180000,
reserved for DSP usage.
this fixes tests/subsys/debug/coredump for this board

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-09-24 09:43:14 -05:00
Mahesh Mahadevan
f75f8bec20 MXRT600: Add DMA support
Add DMA support for MCUX LPC SoC's

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-28 14:24:21 -05:00
Mahesh Mahadevan
fe2b393fff MXRT600: Add support for SPI
Enable access to the arduino pins on the mxrt600 evk board

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-24 16:19:12 -05:00
Hake Huang
93efb9a8f4 dts: enable pit0 in k6s device tree
enable pit0 in NXP k6s

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-08-21 14:27:59 -05:00
Hake Huang
5382673bea counter: add pit in k8s board support
enable frdm_k82f with pit counter driver
this driver can be used as period hardware trigger

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-08-21 14:27:59 -05:00
Manivannan Sadhasivam
0533d4eae1 drivers: serial: Add NXP IUART driver
Add IUART driver based on MCUX SDK. This driver is used to provide
serial console support on i.MX8M Mini SoC.

Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
2020-08-14 14:51:50 -05:00
Manivannan Sadhasivam
8ab4d7d53e dts: arm: nxp: Add i.MX8M Mini devicetree support
Add devicetree support for NXP i.MX8M Mini SoC for utilizing cortex M4
core.

Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
2020-08-14 14:51:50 -05:00
Jiří Keresteš
3a87517c5e drivers: watchdog: mcux_wwdt: add driver for NXP LPC 55xxx WWDT
Adds shim driver for LPC 55xxx Windowed Watchdog Timer (WWDT).

Also updates the "Supported features" table in LPCXpresso55S69
board documentation page.

Fixes #22704.

Signed-off-by: Jiří Keresteš <jiri@kerestes.cz>
2020-08-04 15:13:25 -05:00
Maxime Bittan
adb5dd920b dts: arm: Add I2C nodes for LPC11U6X soc series
This commit adds the device tree nodes and bindings for the I2C
controllers of the LPC11U6X MCUs

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
2020-07-29 20:12:24 +02:00
Simon Guinot
75a2f3e484 dts: lpc11u6x: add node and binding for on-chip EEPROM
This patch adds the DT nodes and binding for the on-chip EEPROM found
on the LPC11U6x MCUs.

Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-07-29 20:12:24 +02:00
Maxime Bittan
5675136eb1 dts: arm: Add UART node and binding for LPC11U6X soc series
This commit adds the UART nodes in the LPC11U6X device tree,
as well as its binding.

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
2020-07-29 20:12:24 +02:00
Simon Guinot
18e4e5c1e2 dts: lpc11u6x: add GPIO node and binding
This patch adds the DT nodes and binding for the GPIO registers found
on the LPC11U6x MCUs.

Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-07-29 20:12:24 +02:00
Maxime Bittan
ed4511ea8c drivers: clock_control: lpc11u6x: Add support for clock controller
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-07-29 20:12:24 +02:00
Maxime Bittan
1724bf49be dts: arm: nxp: Add node and bindings for lpc11u6x clock controller
This commit adds a bindings for the clock controller used in lpc11u6x
MCUs. It also adds a clock-controller node for the lpc11u6x soc series.

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
2020-07-29 20:12:24 +02:00
Simon Guinot
6eb7841bf3 dts: lpc11u6x: add pinmux node and binding
This patch adds the DT nodes and binding for the pinmux registers,
aka IOCON (I/O control), found on the LPC11U6x MCUs.

Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-07-29 20:12:24 +02:00
Maxime Bittan
9931eca5f9 soc: arm: Add basic support for LPC11U6X series
This commit adds basic support for the NXP lpc11u6x soc series.

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
2020-07-29 20:12:24 +02:00
Andrei Gansari
17eca1befd dts: nxp_lpc55S6x_common: revert to flexcomm SS
Disables GPIO CS in order to use Flexcomm's SS as chip select issues
were resolved.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-07-29 08:00:23 -05:00
Mahesh Mahadevan
3ef163ca77 MXRT600: DTS file
Add DTS file to support secure and non-secure access

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-07-28 18:24:19 -05:00
Kumar Gala
77a56fd725 dts: remove incorrect use of device_type property
For true mmio-sram, arc,iccm, arc,dccm nodes we should not be setting
device_type = "memory".  This should be used for true DRAM regions of
memory and not on SoC SRAMs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-07-23 06:37:41 -05:00
Henrik Brix Andersen
c66aca20b4 dts: arm: nxp: ke1xf: add edma devicetree node
Add eDMA devicetree node to the NXP KE1xF SoC devicetree.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-07-21 08:56:51 -05:00
Peter Bigot
9dc7640ede spi-device: set CS gpio flags for all devices that had none
The generic SPI GPIO chip select support now respects devicetree flags
for signal active level.  Update all cs-gpios properties to specify
active low.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-07-09 06:07:07 -05:00
Andrei Gansari
44d32acc43 boards: lpcxpresso55s69 use GPIO as SPI CS
Enable GPIO as a workaround to enable some SPI slaves are not correctly
controlled using the Flexcomm SPI device.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-06-17 08:52:42 +03:00
Hake Huang
5582c2f00b dt-bindings: dts/arm/nxp : add MCUX EDMA Support
add MCUX EDMA support for dts binding

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-06-12 13:03:28 -05:00
Maureen Helm
d9a0dd3967 dts: arm: Add missing adc property for kinetis k8x and kv5x socs
Adds the required #io-channel-cells property to kinetis k8x and kv5x
socs. We are now consistently defining this property for all
nxp,kinetis-adc16 compatible nodes.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 11:01:18 +02:00
Henrik Brix Andersen
784c4728b5 drivers: pwm: mcux_ftm: allow configuring the clock prescaler
Allow configuring the clock prescaler divider for the NXP Kinetis
FlexTimer. Setting the prescaler to a lower value allows for much
higher resolution/accuracy for the generated PWM waveforms.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-05-20 19:03:14 +02:00
Kumar Gala
df56ce3efb drivers: ethernet: mcux: rework how unique mac is determined
Instead of having a Kconfig property, if there is no local-mac-address
property in the devicetree than we'll generate a unique MAC address
based on unique ID registers on the SoC.

We remove the local-mac-address properties in the SoC dtsi files to
match the default behavior that existed before (ie, unique MAC address)

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-09 16:29:57 +02:00
Andrei Gansari
bfbbf92ad5 dts: nxp,lpc-rng binding and lpc55xxx RNG node
Binding used for LPC random number generator hardware.
Describes RNG device node in LPC5xxx SoCs device tree peripherals.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-05-07 23:25:31 -05:00
Alex Porosanu
b1236954e8 boards: frdm_kw41z: enable PWM support
Once the TPM driver and the required configs have been added,
now this patch enables the usage of the PWM framework on KW41Z
SoCs. As such, the DTS gets the proper nodes and the pinmuxing
is done according to the configuration requested.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
2020-05-06 11:33:37 -05:00
Henrik Brix Andersen
25cf045b79 dts: arm: nxp: lpc55S1x: add hs_lspi device node
Add high-speed SPI controller device node to the NXP LPC55S1x SoC
series devicetree.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-05 17:03:29 -05:00
Henrik Brix Andersen
b782b2b7c6 dts: arm: nxp: lpc55S1x: include I2C devicetree header
Include the I2C devicetree header in the NXP LPC55S1x SoC series
devicetree.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-05 17:03:29 -05:00
Henrik Brix Andersen
521b28ecb4 dts: arm: nxp: lpc55S1x: fix interrupts properties for GPIO nodes
Fix the interrupt properties for GPIO nodes for the NXP LPC55S1x SoC
series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-05 17:03:29 -05:00
Henrik Brix Andersen
f66d2fdd83 dts: nxp: k6x: add device tree node for DAC0 and DAC1
Add device tree nodes for the Digital-to-Analog (DAC) modules present
in the NXP Kinetis K6x series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-01 12:35:50 -05:00
Henrik Brix Andersen
44144a2efe dts: nxp: ke1xf: add device tree node for DAC
Add device tree node for the Digital-to-Analog (DAC32) module present
in the NXP Kinetis KE1xF series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-01 12:35:50 -05:00
Henrik Brix Andersen
a5d7946a73 dts: arm: nxp: add initial LPC55S16 devicetree
Add initial devicetree for the NXP LPC55S16. Only non-secure (ns)
access is supported for now.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-01 10:11:01 -05:00
Henrik Brix Andersen
9ceb29ac56 dts: introduce shared binding for the NXP FlexTimer
Do not assume in the SoC level device trees that NXP Kinetis FlexTimer
nodes will always be configured as PWM. Instead, configure FlexTimer
nodes for PWM at the board level for NXP Kinetis boards.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-04-30 08:28:48 -05:00
Kumar Gala
7a15afc1d4 drivers: flash: replace DT_FLASH_DEV_NAME with DT macro
Replace DT_FLASH_DEV_NAME with DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL.
We now set zephyr,flash-controller in the chosen node of the device
tree to the flash controller device.

NOTE: For a SoCs with on die flash, this points to the controller and
      not the 'soc-nv-flash' node.  Typically the controller is the
      parent of the 'soc-nv-flash' node).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-27 18:43:20 -05:00
Kumar Gala
22e65cb9ba gpio: mcux: Convert convert to DT_INST defines
Convert driver to use DT_INST_ defines.  As part of this conversion we
remove the Kconfig options for per GPIO controller enables and instead
get that information from device tree.  This means we now disable each
GPIO controller by default in the DTS and have each board dts enable the
GPIO controller ports it needs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-23 17:07:41 -05:00