/* * Copyright (c) 2020, Linaro Ltd. * * SPDX-License-Identifier: Apache-2.0 */ #include #include #include #include / { aliases { gpio-0 = &gpio0; gpio-1 = &gpio1; }; chosen { zephyr,flash-controller = &iap; }; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-m33f"; reg = <0>; #address-cells = <1>; #size-cells = <1>; mpu: mpu@e000ed90 { compatible = "arm,armv8m-mpu"; reg = <0xe000ed90 0x40>; arm,num-mpu-regions = <8>; }; }; cpu@1 { compatible = "arm,cortex-m33"; reg = <1>; }; }; }; &sram { #address-cells = <1>; #size-cells = <1>; sramx: memory@4000000 { compatible = "mmio-sram"; reg = <0x4000000 DT_SIZE_K(32)>; }; sram0: memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 DT_SIZE_K(64)>; }; sram1: memory@20010000 { compatible = "mmio-sram"; reg = <0x20010000 DT_SIZE_K(64)>; }; sram2: memory@20020000 { compatible = "mmio-sram"; reg = <0x20020000 DT_SIZE_K(64)>; }; sram3: memory@20030000 { compatible = "mmio-sram"; reg = <0x20030000 DT_SIZE_K(64)>; }; sram4: memory@20040000 { /* Conencted to USB bus*/ compatible = "mmio-sram"; reg = <0x20040000 DT_SIZE_K(16)>; }; }; &peripheral { #address-cells = <1>; #size-cells = <1>; iap: flash-controller@34000 { compatible = "nxp,lpc-iap"; label = "FLASH_IAP"; reg = <0x34000 0x18>; #address-cells = <1>; #size-cells = <1>; flash0: flash@0 { compatible = "soc-nv-flash"; label = "MCUX_FLASH"; reg = <0x0 DT_SIZE_K(630)>; erase-block-size = <512>; write-block-size = <512>; }; flash_reserved: flash@9D800 { compatible = "soc-nv-flash"; reg = <0x9D800 DT_SIZE_K(10)>; status = "disabled"; }; boot_rom: flash@3000000 { compatible = "soc-nv-flash"; reg = <0x3000000 DT_SIZE_K(128)>; }; }; gpio0: gpio@0 { compatible = "nxp,lpc-gpio"; reg = <0x8c000 0x2488>; interrupts = <4 2>,<5 2>,<6 2>,<7 2>; label = "GPIO_0"; gpio-controller; #gpio-cells = <2>; }; gpio1: gpio@1 { compatible = "nxp,lpc-gpio"; reg = <0x8c000 0x2488>; interrupts = <32 2>,<33 2>,<34 2>,<35 2>; label = "GPIO_1"; gpio-controller; #gpio-cells = <2>; }; flexcomm0: flexcomm@86000 { compatible = "nxp,lpc-flexcomm"; reg = <0x86000 0x1000>; interrupts = <14 0>; label = "FLEXCOMM_0"; status = "disabled"; }; flexcomm1: flexcomm@87000 { compatible = "nxp,lpc-flexcomm"; reg = <0x87000 0x1000>; interrupts = <15 0>; label = "FLEXCOMM_1"; status = "disabled"; }; flexcomm2: flexcomm@88000 { compatible = "nxp,lpc-flexcomm"; reg = <0x88000 0x1000>; interrupts = <16 0>; label = "FLEXCOMM_2"; status = "disabled"; }; flexcomm3: flexcomm@89000 { compatible = "nxp,lpc-flexcomm"; reg = <0x89000 0x1000>; interrupts = <17 0>; label = "FLEXCOMM_3"; status = "disabled"; }; flexcomm4: flexcomm@8a000 { compatible = "nxp,lpc-flexcomm"; reg = <0x8a000 0x1000>; interrupts = <18 0>; label = "FLEXCOMM_4"; status = "disabled"; }; flexcomm5: flexcomm@96000 { compatible = "nxp,lpc-flexcomm"; reg = <0x96000 0x1000>; interrupts = <19 0>; label = "FLEXCOMM_5"; status = "disabled"; }; flexcomm6: flexcomm@97000 { compatible = "nxp,lpc-flexcomm"; reg = <0x97000 0x1000>; interrupts = <20 0>; label = "FLEXCOMM_6"; status = "disabled"; }; flexcomm7: flexcomm@98000 { compatible = "nxp,lpc-flexcomm"; reg = <0x98000 0x1000>; interrupts = <21 0>; label = "FLEXCOMM_7"; status = "disabled"; }; hs_lspi: spi@9f000 { compatible = "nxp,lpc-spi"; cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, <&gpio1 1 GPIO_ACTIVE_LOW>, <&gpio1 12 GPIO_ACTIVE_LOW>, <&gpio1 26 GPIO_ACTIVE_LOW>; reg = <0x9f000 0x1000>; interrupts = <59 0>; label = "HS_LSPI"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; rng: rng@3a000 { compatible = "nxp,lpc-rng"; reg = <0x3a000 0x1000>; status = "okay"; label = "RNG"; }; }; &nvic { arm,num-irq-priority-bits = <3>; };