mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-06 04:45:09 +00:00
d42f10eac1
Add support DAC driver for ek_ra8m1, ek_ra8d1, mck_ra8t1, ek_ra6m5, ek_ra6m4, ek_ra6m3, ek_ra6m2, ek_ra6m1, ek_ra6e2, fpb_ra6e2, fpb_ra6e1, ek_ra4m3, ek_ra4m2, ek_ra4e2, ek_ra2a1 Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
58 lines
1.1 KiB
Plaintext
58 lines
1.1 KiB
Plaintext
/*
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* Copyright (c) 2024-2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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sci0_default: sci0_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>,
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<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
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};
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};
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spi0_default: spi0_default {
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group1 {
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/* MISO MOSI RSPCK SSL */
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psels = <RA_PSEL(RA_PSEL_SPI, 1, 10)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 9)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 11)>,
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<RA_PSEL(RA_PSEL_SPI, 3, 1)>;
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};
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};
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canfd0_default: canfd0_default {
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group1 {
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/* CRX0 CTX0 */
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psels = <RA_PSEL(RA_PSEL_CANFD, 4, 2)>,
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<RA_PSEL(RA_PSEL_CANFD, 4, 1)>;
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drive-strength = "high";
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};
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};
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adc0_default: adc0_default {
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group1 {
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/* input */
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psels = <RA_PSEL(RA_PSEL_ADC, 0, 0)>;
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renesas,analog-enable;
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};
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};
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dac0_default: dac0_default {
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group1 {
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/* output */
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psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
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renesas,analog-enable;
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};
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};
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pwm1_default: pwm1_default {
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group1 {
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/* GTIOC1A GTIOC1B */
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psels = <RA_PSEL(RA_PSEL_GPT1, 4, 9)>,
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<RA_PSEL(RA_PSEL_GPT1, 4, 8)>;
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};
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};
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};
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