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https://github.com/zephyrproject-rtos/zephyr
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The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and MCLK. The old devices had defined the peripheral clock enable bit at PM. On the newer devices this was extracted on a dedicated memory section called Master Clock (MCLK). This change excludes the dedicated bindings in favor of a generic approach that cover all cases. Now the clocks properties is complemented by the atmel,assigned-clocks property. It gives the liberty to user to customize the clock source from a generic clock or configure the direct connections. All peripherals drivers were reworked with the newer solution. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
/*
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* Copyright (c) 2020 Google LLC.
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* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam0_dac
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#include <errno.h>
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#include <zephyr/drivers/dac.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(dac_sam0, CONFIG_DAC_LOG_LEVEL);
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/* clang-format off */
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/*
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* Maps between the DTS reference property names and register values. Note that
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* the ASF uses the 09/2015 names which differ from the 03/2020 datasheet.
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*
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* TODO(#21273): replace once improved support for enum values lands.
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*/
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#define SAM0_DAC_REFSEL_0 DAC_CTRLB_REFSEL_INT1V_Val
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#define SAM0_DAC_REFSEL_1 DAC_CTRLB_REFSEL_AVCC_Val
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#define SAM0_DAC_REFSEL_2 DAC_CTRLB_REFSEL_VREFP_Val
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struct dac_sam0_cfg {
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Dac *regs;
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const struct pinctrl_dev_config *pcfg;
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volatile uint32_t *mclk;
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uint32_t mclk_mask;
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uint32_t gclk_gen;
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uint16_t gclk_id;
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uint8_t refsel;
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};
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/* Write to the DAC. */
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static int dac_sam0_write_value(const struct device *dev, uint8_t channel,
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uint32_t value)
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{
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const struct dac_sam0_cfg *const cfg = dev->config;
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Dac *regs = cfg->regs;
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if (value >= BIT(12)) {
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LOG_ERR("value %d out of range", value);
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return -EINVAL;
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}
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regs->DATA.reg = (uint16_t)value;
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return 0;
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}
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/*
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* Setup the channel. As the SAM0 has one fixed width channel, this validates
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* the input and does nothing else.
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*/
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static int dac_sam0_channel_setup(const struct device *dev,
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const struct dac_channel_cfg *channel_cfg)
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{
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if (channel_cfg->channel_id != 0) {
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return -EINVAL;
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}
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if (channel_cfg->resolution != 10) {
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return -ENOTSUP;
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}
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if (channel_cfg->internal) {
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return -ENOSYS;
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}
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return 0;
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}
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/* Initialise and enable the DAC. */
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static int dac_sam0_init(const struct device *dev)
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{
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const struct dac_sam0_cfg *const cfg = dev->config;
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Dac *regs = cfg->regs;
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int retval;
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*cfg->mclk |= cfg->mclk_mask;
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#ifdef MCLK
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GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
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| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
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#else
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
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| GCLK_CLKCTRL_GEN(cfg->gclk_gen)
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| GCLK_CLKCTRL_ID(cfg->gclk_id);
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#endif
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retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (retval < 0) {
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return retval;
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}
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/* Reset then configure the DAC */
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regs->CTRLA.bit.SWRST = 1;
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while (regs->STATUS.bit.SYNCBUSY) {
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}
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regs->CTRLB.bit.REFSEL = cfg->refsel;
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regs->CTRLB.bit.EOEN = 1;
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/* Enable */
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regs->CTRLA.bit.ENABLE = 1;
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while (regs->STATUS.bit.SYNCBUSY) {
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}
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return 0;
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}
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static DEVICE_API(dac, api_sam0_driver_api) = {
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.channel_setup = dac_sam0_channel_setup,
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.write_value = dac_sam0_write_value
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};
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#define ASSIGNED_CLOCKS_CELL_BY_NAME \
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ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
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#define SAM0_DAC_REFSEL(n) \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(n, reference), \
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(DT_INST_ENUM_IDX(n, reference)), (0))
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#define SAM0_DAC_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static const struct dac_sam0_cfg dac_sam0_cfg_##n = { \
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.regs = (Dac *)DT_INST_REG_ADDR(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
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.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
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.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
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.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit), \
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.refsel = UTIL_CAT(SAM0_DAC_REFSEL_, SAM0_DAC_REFSEL(n)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &dac_sam0_init, NULL, NULL, \
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&dac_sam0_cfg_##n, POST_KERNEL, \
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CONFIG_DAC_INIT_PRIORITY, \
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&api_sam0_driver_api)
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DT_INST_FOREACH_STATUS_OKAY(SAM0_DAC_INIT);
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/* clang-format on */
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