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https://github.com/zephyrproject-rtos/zephyr
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4044e0e75c
RP2350 provides a function to get OTP-backed chip ID. Prefer using this on supported platforms for these reasons: - a secure internal identifier, same as read by picotool - works on flashless boards - does not conflict with code running in XIP mode (e.g. when the other core tries to access device ID) - when used with USB HWID serial number will match one BootROM has Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com> Co-authored-by: Alexander Wachter <alexander@wachter.cloud>
122 lines
3.1 KiB
C
122 lines
3.1 KiB
C
/*
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* Copyright (c) 2022 Yonatan Schachter
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* Copyright (c) 2024 Andrew Featherstone
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <zephyr/drivers/hwinfo.h>
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#include <hardware/flash.h>
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#if defined(CONFIG_SOC_SERIES_RP2040)
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#include <hardware/structs/vreg_and_chip_reset.h>
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#else
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#include <zephyr/sys/byteorder.h>
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#include <pico/bootrom.h>
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#include <hardware/structs/powman.h>
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#endif
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#define FLASH_RUID_DATA_BYTES 8
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#if defined(CONFIG_SOC_SERIES_RP2040)
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#define HAD_RUN_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB)
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#define HAD_PSM_RESTART_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB)
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#define HAD_POR_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB)
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#else
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#define HAD_RUN_BIT BIT(POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB)
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#define HAD_PSM_RESTART_BIT BIT(POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB)
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#define HAD_POR_BIT BIT(POWMAN_CHIP_RESET_HAD_POR_LSB)
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#endif
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ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
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{
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uint8_t id[FLASH_RUID_DATA_BYTES];
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#if CONFIG_HWINFO_RPI_PICO_CHIP_ID
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rom_get_sys_info_fn get_sys_info = (rom_get_sys_info_fn)
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rom_func_lookup_inline(ROM_FUNC_GET_SYS_INFO);
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/* Words: CHIP_INFO, PACKAGE_SEL, DEVICE_ID, WAFER_ID */
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uint32_t words[4];
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int n = get_sys_info(words, ARRAY_SIZE(words), SYS_INFO_CHIP_INFO);
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/* CHIP_INFO returns 4 words */
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__ASSERT(n == ARRAY_SIZE(words), "Failed to get chip info");
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/* Use DEVICE_ID + WAFER_ID, like BootROM uses for its USB ID */
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sys_put_be(id, &words[2], 2 * sizeof(uint32_t));
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#else
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uint32_t key;
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/*
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* flash_get_unique_id temporarily disables XIP to query the
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* flash for its ID. If the CPU is interrupted while XIP is
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* disabled, it will halt. Therefore, interrupts must be disabled
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* before fetching the ID.
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*/
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key = irq_lock();
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flash_get_unique_id(id);
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irq_unlock(key);
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#endif /* defined(CONFIG_SOC_SERIES_RP2350) */
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if (length > sizeof(id)) {
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length = sizeof(id);
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}
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memcpy(buffer, id, length);
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return length;
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}
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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uint32_t flags = 0;
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#if defined(CONFIG_SOC_SERIES_RP2040)
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uint32_t reset_register = vreg_and_chip_reset_hw->chip_reset;
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#else
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uint32_t reset_register = powman_hw->chip_reset;
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#endif
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if (reset_register & HAD_POR_BIT) {
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flags |= RESET_POR;
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}
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if (reset_register & HAD_RUN_BIT) {
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flags |= RESET_PIN;
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}
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if (reset_register & HAD_PSM_RESTART_BIT) {
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flags |= RESET_DEBUG;
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}
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#if defined(CONFIG_SOC_SERIES_RP2350)
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if (reset_register & POWMAN_CHIP_RESET_HAD_BOR_BITS) {
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flags |= RESET_BROWNOUT;
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}
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if (reset_register & (POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS |
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POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_BITS |
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POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_BITS |
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POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_BITS)) {
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flags |= RESET_WATCHDOG;
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}
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#endif
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*cause = flags;
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return 0;
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}
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int z_impl_hwinfo_clear_reset_cause(void)
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{
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/* The reset register can't be modified, nothing to do. */
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return -ENOSYS;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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*supported = RESET_PIN | RESET_DEBUG | RESET_POR;
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#if defined(CONFIG_SOC_SERIES_RP2350)
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*supported |= RESET_BROWNOUT | RESET_WATCHDOG;
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#endif
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return 0;
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}
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