mirror of
https://github.com/zephyrproject-rtos/zephyr
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9c436baf85
Modified pinctrl driver to configure analog pins for ULP and HP modes. Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
/*
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* Copyright (c) 2023 Antmicro
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* Copyright (c) 2024 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT silabs_siwx91x_pinctrl
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#include <zephyr/drivers/pinctrl.h>
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#include "sl_si91x_peripheral_gpio.h"
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#define MODE_COUNT 16
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#define HP_PERIPHERAL_ON_ULP_PIN 6
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#define HP_ANALOG_MODE 14
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#define ULP_ANALOG_MODE 7
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static bool pinctrl_siwx91x_valid_mode(uint8_t mode)
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{
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return mode < MODE_COUNT;
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}
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static void pinctrl_siwx91x_set(uint8_t port, uint8_t pin, uint8_t ulppin, uint8_t mode,
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uint8_t ulpmode, uint8_t pad)
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{
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if (pad == 0) {
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sl_si91x_gpio_enable_host_pad_selection((port << 4) | pin);
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} else if (pad != 0xFF && pad != 9) {
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sl_si91x_gpio_enable_pad_selection(pad);
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}
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if (port == SL_GPIO_ULP_PORT) {
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if (ulpmode != ULP_ANALOG_MODE) {
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sl_si91x_gpio_enable_ulp_pad_receiver(ulppin);
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} else {
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sl_si91x_gpio_disable_ulp_pad_receiver(ulppin);
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}
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} else {
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if (mode != HP_ANALOG_MODE) {
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sl_si91x_gpio_enable_pad_receiver((port << 4) | pin);
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} else {
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sl_si91x_gpio_disable_pad_receiver((port << 4) | pin);
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}
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}
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if (pinctrl_siwx91x_valid_mode(mode)) {
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GPIO->PIN_CONFIG[(port << 4) | pin].GPIO_CONFIG_REG_b.MODE = mode;
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}
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if (pinctrl_siwx91x_valid_mode(ulpmode)) {
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if (pinctrl_siwx91x_valid_mode(mode) && ulpmode != HP_PERIPHERAL_ON_ULP_PIN) {
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sl_si91x_gpio_ulp_soc_mode(ulppin, ulpmode);
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ulpmode = 0;
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}
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ULP_GPIO->PIN_CONFIG[ulppin].GPIO_CONFIG_REG_b.MODE = ulpmode;
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}
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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int i;
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for (i = 0; i < pin_cnt; i++) {
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pinctrl_siwx91x_set(pins[i].port, pins[i].pin, pins[i].ulppin, pins[i].mode,
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pins[i].ulpmode, pins[i].pad);
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}
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return 0;
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}
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