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Two DMA channels are assigned to TX and RX respectively: - A TX DMA request is asserted when there is space in the FIFO. - A RX DMA request is asserted when data is in the FIFO. When DMA is enabled for a peripheral, the DMA transfer completion is signaled on the peripheral's interrupt only (here UART's interrupt). It is not signaled on the DMA dedicated interrupt. Also, when DMA is enabled for a peripheral, the DMA controller stops the normal transfer interrupts for this peripheral from reaching the NVIC (the interrupts are still reported in the interrupt registers of the peripheral). Thus, when a large amount of data is transferred using DMA, instead of receiving multiple interrupts from the peripheral as data flows, the NVIC receives only one interrupt when the transfer completes (unmasked peripheral error interrupts continue to be sent to the NVIC). Signed-off-by: Julien Panis <jpanis@baylibre.com>
24 lines
608 B
Plaintext
24 lines
608 B
Plaintext
# Copyright (c) 2024 Texas Instruments Incorporated
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# Copyright (c) 2024 BayLibre, SAS
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#
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# SPDX-License-Identifier: Apache-2.0
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config UART_CC23X0
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bool "TI SimpleLink CC23x0 UART driver"
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default y
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depends on DT_HAS_TI_CC23X0_UART_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select SERIAL_SUPPORT_ASYNC
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select PINCTRL
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help
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Enable the TI SimpleLink CC23x0 UART driver.
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config UART_CC23X0_DMA_DRIVEN
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bool "DMA support for TI CC23X0 UART devices"
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depends on UART_CC23X0
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depends on UART_ASYNC_API
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select DMA
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help
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DMA driven mode offloads data transfer tasks from the CPU.
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