mirror of
https://github.com/zephyrproject-rtos/zephyr
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1a7eb61f02
Use DEVICE_API macro to place driver API instances into a linker section. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
129 lines
4.4 KiB
C
129 lines
4.4 KiB
C
/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_rx_uart_sci_qemu
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#include <zephyr/drivers/uart.h>
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#include <soc.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(renesas_rx_uart_sci_qemu, CONFIG_UART_LOG_LEVEL);
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#define REG_MASK(reg) (BIT_MASK(_CONCAT(reg, _LEN)) << _CONCAT(reg, _POS))
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/* Registers */
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#define SMR 0x00 /*!< Serial Mode Register */
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#define BRR 0x01 /*!< Bit Rate Register */
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#define SCR 0x02 /*!< Serial Control Register */
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#define TDR 0x03 /*!< Transmit Data Register */
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#define SSR 0x04 /*!< Serial Status Register */
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#define RDR 0x05 /*!< Receive Data Register */
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/**
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* SSR (Serial Status Register)
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*
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* - MPBT[0..1]: Multi-Processor Bit Transfer
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* - MPB[1..2]: Multi-Processor
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* - TEND[2..3]: Transmit End Flag
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* - PER[3..4]: Parity Error Flag
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* - FER[4..5]: Framing Error Flag
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* - ORER[5..6]: Overrun Error Flag
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* - RDRF[6..7]: Receive Data Full Flag
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* - TDRE[7..8]: Transmit Data Empty Flag
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*/
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#define SSR_MPBT_POS (0)
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#define SSR_MPBT_LEN (1)
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#define SSR_MPB_POS (1)
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#define SSR_MPB_LEN (1)
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#define SSR_TEND_POS (2)
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#define SSR_TEND_LEN (1)
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#define SSR_PER_POS (3)
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#define SSR_PER_LEN (1)
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#define SSR_FER_POS (4)
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#define SSR_FER_LEN (1)
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#define SSR_ORER_POS (5)
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#define SSR_ORER_LEN (1)
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#define SSR_RDRF_POS (6)
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#define SSR_RDRF_LEN (1)
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#define SSR_TDRE_POS (7)
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#define SSR_TDRE_LEN (1)
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#define SCI_SCR_RE (1 << 4)
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struct uart_renesas_rx_sci_qemu_cfg {
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mem_addr_t regs;
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};
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struct uart_renesas_rx_sci_qemu_data {
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const struct device *dev;
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struct uart_config uart_config;
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};
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static uint8_t uart_renesas_rx_qemu_read_8(const struct device *dev, uint32_t offs)
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{
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const struct uart_renesas_rx_sci_qemu_cfg *config = dev->config;
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return sys_read8(config->regs + offs);
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}
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static void uart_renesas_rx_qemu_write_8(const struct device *dev, uint32_t offs, uint8_t value)
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{
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const struct uart_renesas_rx_sci_qemu_cfg *config = dev->config;
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sys_write8(value, config->regs + offs);
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}
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static int uart_renesas_rx_sci_qemu_poll_in(const struct device *dev, unsigned char *c)
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{
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uart_renesas_rx_qemu_write_8(dev, SCR, SCI_SCR_RE);
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if ((uart_renesas_rx_qemu_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {
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/* There are no characters available to read. */
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return -1;
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}
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*c = uart_renesas_rx_qemu_read_8(dev, RDR);
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return 0;
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}
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static void uart_renesas_rx_sci_qemu_poll_out(const struct device *dev, unsigned char c)
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{
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while (!(uart_renesas_rx_qemu_read_8(dev, SSR) & REG_MASK(SSR_TEND))) {
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}
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uart_renesas_rx_qemu_write_8(dev, TDR, c);
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}
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static DEVICE_API(uart, uart_rx_driver_api) = {
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.poll_in = uart_renesas_rx_sci_qemu_poll_in,
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.poll_out = uart_renesas_rx_sci_qemu_poll_out,
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};
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/* Device Instantiation */
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#define UART_RENESAS_RX_SCI_QEMU_CFG_INIT(n) \
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static const struct uart_renesas_rx_sci_qemu_cfg uart_rx_sci_cfg_##n = { \
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.regs = DT_REG_ADDR(DT_INST_PARENT(n)), \
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}
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#define UART_RENESAS_RX_SCI_QEMU_INIT(n) \
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UART_RENESAS_RX_SCI_QEMU_CFG_INIT(n); \
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\
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static struct uart_renesas_rx_sci_qemu_data uart_rx_sci_data_##n = { \
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.uart_config = \
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{ \
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.baudrate = DT_INST_PROP(n, current_speed), \
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.parity = UART_CFG_PARITY_NONE, \
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.stop_bits = UART_CFG_STOP_BITS_1, \
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.data_bits = UART_CFG_DATA_BITS_8, \
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.flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, NULL, NULL, &uart_rx_sci_data_##n, &uart_rx_sci_cfg_##n, \
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PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &uart_rx_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(UART_RENESAS_RX_SCI_QEMU_INIT)
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