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https://github.com/zephyrproject-rtos/zephyr
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e50851d476
When lazy HiFi context switching is enabled, the system starts with the HiFi coprocessor disabled. Should the thread use that coprocessor, it will generate an exception which in turn will enable the coprocessor and save/restore the HiFi registers as appropriate. When switching to a new thread, the HiFi coprocessor is again disabled. For simplicity, there are no restrictions as to which thread is allowed to use the coprocessor. Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
/**
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* Copyright (c) 2024 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <kswap.h>
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#include <ksched.h>
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#include <ipi.h>
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#ifdef CONFIG_TRACE_SCHED_IPI
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extern void z_trace_sched_ipi(void);
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#endif
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void flag_ipi(uint32_t ipi_mask)
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{
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#if defined(CONFIG_SCHED_IPI_SUPPORTED)
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if (arch_num_cpus() > 1) {
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atomic_or(&_kernel.pending_ipi, (atomic_val_t)ipi_mask);
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}
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#endif /* CONFIG_SCHED_IPI_SUPPORTED */
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}
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/* Create a bitmask of CPUs that need an IPI. Note: sched_spinlock is held. */
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atomic_val_t ipi_mask_create(struct k_thread *thread)
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{
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if (!IS_ENABLED(CONFIG_IPI_OPTIMIZE)) {
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return (CONFIG_MP_MAX_NUM_CPUS > 1) ? IPI_ALL_CPUS_MASK : 0;
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}
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uint32_t ipi_mask = 0;
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uint32_t num_cpus = (uint32_t)arch_num_cpus();
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uint32_t id = _current_cpu->id;
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struct k_thread *cpu_thread;
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bool executable_on_cpu = true;
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for (uint32_t i = 0; i < num_cpus; i++) {
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if (id == i) {
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continue;
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}
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/*
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* An IPI absolutely does not need to be sent if ...
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* 1. the CPU is not active, or
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* 2. <thread> can not execute on the target CPU
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* ... and might not need to be sent if ...
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* 3. the target CPU's active thread is not preemptible, or
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* 4. the target CPU's active thread has a higher priority
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* (Items 3 & 4 may be overridden by a metaIRQ thread)
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*/
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#if defined(CONFIG_SCHED_CPU_MASK)
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executable_on_cpu = ((thread->base.cpu_mask & BIT(i)) != 0);
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#endif
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cpu_thread = _kernel.cpus[i].current;
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if ((cpu_thread != NULL) &&
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(((z_sched_prio_cmp(cpu_thread, thread) < 0) &&
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(thread_is_preemptible(cpu_thread))) ||
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thread_is_metairq(thread)) && executable_on_cpu) {
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ipi_mask |= BIT(i);
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}
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}
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return (atomic_val_t)ipi_mask;
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}
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void signal_pending_ipi(void)
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{
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/* Synchronization note: you might think we need to lock these
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* two steps, but an IPI is idempotent. It's OK if we do it
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* twice. All we require is that if a CPU sees the flag true,
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* it is guaranteed to send the IPI, and if a core sets
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* pending_ipi, the IPI will be sent the next time through
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* this code.
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*/
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#if defined(CONFIG_SCHED_IPI_SUPPORTED)
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if (arch_num_cpus() > 1) {
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uint32_t cpu_bitmap;
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cpu_bitmap = (uint32_t)atomic_clear(&_kernel.pending_ipi);
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if (cpu_bitmap != 0) {
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#ifdef CONFIG_ARCH_HAS_DIRECTED_IPIS
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arch_sched_directed_ipi(cpu_bitmap);
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#else
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arch_sched_broadcast_ipi();
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#endif
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}
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}
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#endif /* CONFIG_SCHED_IPI_SUPPORTED */
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}
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void z_sched_ipi(void)
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{
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/* NOTE: When adding code to this, make sure this is called
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* at appropriate location when !CONFIG_SCHED_IPI_SUPPORTED.
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*/
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#ifdef CONFIG_TRACE_SCHED_IPI
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z_trace_sched_ipi();
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#endif /* CONFIG_TRACE_SCHED_IPI */
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#ifdef CONFIG_TIMESLICING
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if (thread_is_sliceable(_current)) {
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z_time_slice();
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}
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#endif /* CONFIG_TIMESLICING */
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#ifdef CONFIG_ARCH_IPI_LAZY_COPROCESSORS_SAVE
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arch_ipi_lazy_coprocessors_save();
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#endif
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}
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