mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-03 01:21:57 +00:00
ac74d8b652
Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
/* spi_dw_regs.h - Designware SPI driver private definitions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SPI_DW_REGS_H__
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#define __SPI_DW_REGS_H__
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#define DW_SPI_REG_CTRLR0 (0x00)
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#define DW_SPI_REG_CTRLR1 (0x04)
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#define DW_SPI_REG_SSIENR (0x08)
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#define DW_SPI_REG_MWCR (0x0c)
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#define DW_SPI_REG_SER (0x10)
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#define DW_SPI_REG_BAUDR (0x14)
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#define DW_SPI_REG_TXFTLR (0x18)
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#define DW_SPI_REG_RXFTLR (0x1c)
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#define DW_SPI_REG_TXFLR (0x20)
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#define DW_SPI_REG_RXFLR (0x24)
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#define DW_SPI_REG_SR (0x28)
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#define DW_SPI_REG_IMR (0x2c)
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#define DW_SPI_REG_ISR (0x30)
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#define DW_SPI_REG_RISR (0x34)
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#define DW_SPI_REG_TXOICR (0x38)
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#define DW_SPI_REG_RXOICR (0x3c)
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#define DW_SPI_REG_RXUICR (0x40)
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#define DW_SPI_REG_MSTICR (0x44)
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#define DW_SPI_REG_ICR (0x48)
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#define DW_SPI_REG_DMACR (0x4c)
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#define DW_SPI_REG_DMATDLR (0x50)
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#define DW_SPI_REG_DMARDLR (0x54)
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#define DW_SPI_REG_IDR (0x58)
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#define DW_SPI_REG_SSI_COMP_VERSION (0x5c)
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#define DW_SPI_REG_DR (0x60)
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#define DW_SPI_REG_RX_SAMPLE_DLY (0xf0)
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#define DW_SSI_COMP_VERSION (0x3332332a)
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/* Register helpers */
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DEFINE_MM_REG_WRITE(ctrlr0, DW_SPI_REG_CTRLR0, 32)
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DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 8)
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DEFINE_MM_REG_WRITE(txftlr, DW_SPI_REG_TXFTLR, 32)
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DEFINE_MM_REG_WRITE(rxftlr, DW_SPI_REG_RXFTLR, 32)
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DEFINE_MM_REG_READ(rxftlr, DW_SPI_REG_RXFTLR, 32)
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DEFINE_MM_REG_READ(txftlr, DW_SPI_REG_TXFTLR, 32)
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DEFINE_MM_REG_WRITE(dr, DW_SPI_REG_DR, 32)
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DEFINE_MM_REG_READ(dr, DW_SPI_REG_DR, 32)
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DEFINE_MM_REG_READ(ssi_comp_version, DW_SPI_REG_SSI_COMP_VERSION, 32)
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/* ICR is on a unique bit */
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DEFINE_TEST_BIT_OP(icr, DW_SPI_REG_ICR, DW_SPI_SR_ICR_BIT)
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#define clear_interrupts(addr) test_bit_icr(addr)
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#ifdef CONFIG_SPI_DW_CLOCK_GATE
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static inline void _clock_config(struct device *dev)
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{
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struct device *clk;
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char *drv = CONFIG_SPI_DW_CLOCK_GATE_DRV_NAME;
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clk = device_get_binding(drv);
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if (clk) {
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struct spi_dw_data *spi = dev->driver_data;
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spi->clock = clk;
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}
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}
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static inline void _clock_on(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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clock_control_on(spi->clock, info->clock_data);
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}
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static inline void _clock_off(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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clock_control_off(spi->clock, info->clock_data);
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}
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#else
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#define _clock_config(...)
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#define _clock_on(...)
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#define _clock_off(...)
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#endif /* CONFIG_SPI_DW_CLOCK_GATE */
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#endif /* __SPI_DW_REGS_H__ */
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