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https://github.com/zephyrproject-rtos/zephyr
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749d2d21bf
This commit adds driver support for DMA on f0/f1/f2/f3/f4/l0/l4 series stm32. Notice due to some bugs, this is currently not working with f7. There are two kinds of IP blocks are used across these stm32, one is the one that has been used on F2/F4/F7 series, and the other one is the one that has been used on F0/F1/F3/L0/L4 series. Memory to memory transfer is only supported on the second DMA on F2/F4 with 'st,mem2mem' to be declared in dts. This driver depends on k_malloc to allocate memory for stream instances, so CONFIG_HEAP_MEM_POOL_SIZE must be big enough to hold them. Common parts of the driver are in dma_stm32.c and SoC related parts are implemented in dma_stm32_v*.c. This driver has been tested on multiple nucleo boards, including NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/L073RZ/L476RG with the loop_transfer and chan_blen_transfer test cases. Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
154 lines
3.2 KiB
C
154 lines
3.2 KiB
C
/*
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* Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief DMA low level driver implementation for F0/F1/F3/L0/L4 series SoCs.
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*/
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#include <drivers/dma.h>
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#include <soc.h>
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#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(dma_stm32_v2);
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u32_t table_ll_stream[] = {
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LL_DMA_CHANNEL_1,
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LL_DMA_CHANNEL_2,
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LL_DMA_CHANNEL_3,
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LL_DMA_CHANNEL_4,
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LL_DMA_CHANNEL_5,
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LL_DMA_CHANNEL_6,
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LL_DMA_CHANNEL_7,
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};
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void (*func_ll_clear_ht[])(DMA_TypeDef *DMAx) = {
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LL_DMA_ClearFlag_HT1,
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LL_DMA_ClearFlag_HT2,
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LL_DMA_ClearFlag_HT3,
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LL_DMA_ClearFlag_HT4,
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LL_DMA_ClearFlag_HT5,
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LL_DMA_ClearFlag_HT6,
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LL_DMA_ClearFlag_HT7,
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};
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void (*func_ll_clear_tc[])(DMA_TypeDef *DMAx) = {
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LL_DMA_ClearFlag_TC1,
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LL_DMA_ClearFlag_TC2,
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LL_DMA_ClearFlag_TC3,
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LL_DMA_ClearFlag_TC4,
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LL_DMA_ClearFlag_TC5,
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LL_DMA_ClearFlag_TC6,
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LL_DMA_ClearFlag_TC7,
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};
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u32_t (*func_ll_is_active_ht[])(DMA_TypeDef *DMAx) = {
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LL_DMA_IsActiveFlag_HT1,
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LL_DMA_IsActiveFlag_HT2,
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LL_DMA_IsActiveFlag_HT3,
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LL_DMA_IsActiveFlag_HT4,
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LL_DMA_IsActiveFlag_HT5,
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LL_DMA_IsActiveFlag_HT6,
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LL_DMA_IsActiveFlag_HT7,
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};
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u32_t (*func_ll_is_active_tc[])(DMA_TypeDef *DMAx) = {
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LL_DMA_IsActiveFlag_TC1,
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LL_DMA_IsActiveFlag_TC2,
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LL_DMA_IsActiveFlag_TC3,
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LL_DMA_IsActiveFlag_TC4,
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LL_DMA_IsActiveFlag_TC5,
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LL_DMA_IsActiveFlag_TC6,
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LL_DMA_IsActiveFlag_TC7,
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};
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static void (*func_ll_clear_te[])(DMA_TypeDef *DMAx) = {
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LL_DMA_ClearFlag_TE1,
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LL_DMA_ClearFlag_TE2,
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LL_DMA_ClearFlag_TE3,
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LL_DMA_ClearFlag_TE4,
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LL_DMA_ClearFlag_TE5,
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LL_DMA_ClearFlag_TE6,
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LL_DMA_ClearFlag_TE7,
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};
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static void (*func_ll_clear_gi[])(DMA_TypeDef *DMAx) = {
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LL_DMA_ClearFlag_GI1,
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LL_DMA_ClearFlag_GI2,
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LL_DMA_ClearFlag_GI3,
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LL_DMA_ClearFlag_GI4,
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LL_DMA_ClearFlag_GI5,
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LL_DMA_ClearFlag_GI6,
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LL_DMA_ClearFlag_GI7,
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};
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static u32_t (*func_ll_is_active_te[])(DMA_TypeDef *DMAx) = {
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LL_DMA_IsActiveFlag_TE1,
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LL_DMA_IsActiveFlag_TE2,
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LL_DMA_IsActiveFlag_TE3,
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LL_DMA_IsActiveFlag_TE4,
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LL_DMA_IsActiveFlag_TE5,
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LL_DMA_IsActiveFlag_TE6,
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LL_DMA_IsActiveFlag_TE7,
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};
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static u32_t (*func_ll_is_active_gi[])(DMA_TypeDef *DMAx) = {
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LL_DMA_IsActiveFlag_GI1,
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LL_DMA_IsActiveFlag_GI2,
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LL_DMA_IsActiveFlag_GI3,
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LL_DMA_IsActiveFlag_GI4,
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LL_DMA_IsActiveFlag_GI5,
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LL_DMA_IsActiveFlag_GI6,
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LL_DMA_IsActiveFlag_GI7,
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};
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void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, u32_t id)
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{
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LOG_INF("tc: %d, ht: %d, te: %d, gi: %d",
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func_ll_is_active_tc[id](dma),
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func_ll_is_active_ht[id](dma),
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func_ll_is_active_te[id](dma),
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func_ll_is_active_gi[id](dma));
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}
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void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, u32_t id)
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{
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func_ll_clear_te[id](dma);
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func_ll_clear_gi[id](dma);
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}
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bool stm32_dma_is_irq_happened(DMA_TypeDef *dma, u32_t id)
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{
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if (func_ll_is_active_te[id](dma)) {
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return true;
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}
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return false;
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}
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bool stm32_dma_is_unexpected_irq_happened(DMA_TypeDef *dma, u32_t id)
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{
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/* Preserve for future amending. */
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return false;
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}
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void stm32_dma_enable_stream(DMA_TypeDef *dma, u32_t id)
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{
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LL_DMA_EnableChannel(dma, table_ll_stream[id]);
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}
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int stm32_dma_disable_stream(DMA_TypeDef *dma, u32_t id)
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{
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if (!LL_DMA_IsEnabledChannel(dma, table_ll_stream[id])) {
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return 0;
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}
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LL_DMA_DisableChannel(dma, table_ll_stream[id]);
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return -EAGAIN;
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}
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