zephyr/dts/arm/96b_neonkey.fixup
Manivannan Sadhasivam 52daa75ea0 boards: arm: Add support for 96Boards Neonkey Board
This patch adds support for 96Boards Neonkey Mezzanine
board.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2017-10-18 10:25:43 -05:00

39 lines
2.4 KiB
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/* This file is a temporary workaround for mapping of the generated information
* to the current driver definitions. This will be removed when the drivers
* are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions.
*/
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40011000_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40011000_CURRENT_SPEED
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40011000_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_PORT_1_NAME ST_STM32_USART_40011000_LABEL
#define PORT_1_IRQ ST_STM32_USART_40011000_IRQ_0
#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V1_40005400_BASE_ADDRESS
#define CONFIG_I2C_1_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
#define CONFIG_I2C_1_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_1_NAME ST_STM32_I2C_V1_40005400_LABEL
#define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V1_40005400_IRQ_EVENT
#define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V1_40005400_IRQ_ERROR
#define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
#define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V1_40005800_BASE_ADDRESS
#define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
#define CONFIG_I2C_2_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_2_NAME ST_STM32_I2C_V1_40005800_LABEL
#define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V1_40005800_IRQ_EVENT
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V1_40005800_IRQ_ERROR
#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
#define CONFIG_I2C_3_BASE_ADDRESS ST_STM32_I2C_V1_40005C00_BASE_ADDRESS
#define CONFIG_I2C_3_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY
#define CONFIG_I2C_3_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005C00_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_3_NAME ST_STM32_I2C_V1_40005C00_LABEL
#define CONFIG_I2C_3_EVENT_IRQ ST_STM32_I2C_V1_40005C00_IRQ_EVENT
#define CONFIG_I2C_3_ERROR_IRQ ST_STM32_I2C_V1_40005C00_IRQ_ERROR
#define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY