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zephyr/boards/riscv
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Andrew Boie a9670ab5cf boards: centralize QEMU icount management 
Instead of endlessly repeating the same command line args,
centralize this and tune the shift value on a per-board
basis.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-24 20:28:36 -04:00
..
hifive1 boards: centralize QEMU icount management 2020-06-24 20:28:36 -04:00
hifive1_revb
litex_vexriscv
m2gl025_miv drivers: uart: miv: convert to DT_INST defines 2020-03-11 16:37:22 -06:00
qemu_riscv32 boards: centralize QEMU icount management 2020-06-24 20:28:36 -04:00
qemu_riscv64 boards: centralize QEMU icount management 2020-06-24 20:28:36 -04:00
rv32m1_vega boards: riscv: Conditionalize pinmuxes on rv32m1_vega board 2020-05-22 14:51:07 +02:00
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