mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 23:51:56 +00:00
732424f065
Change the common "init with 0" + "give" idiom to "init with 1". This
won't change the behavior or performance, but should decrease the size
ever so slightly.
This change has been performed mechanically with the following
Coccinelle script:
@@
expression SEM;
expression LIMIT;
expression TIMEOUT;
@@
- k_sem_init(SEM, 0, LIMIT);
- k_sem_give(SEM);
+ k_sem_init(SEM, 1, LIMIT);
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
406 lines
10 KiB
C
406 lines
10 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/ioapic.h>
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#include <gpio.h>
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#include <init.h>
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#include <sys_io.h>
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#include <misc/util.h>
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#include "qm_gpio.h"
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#include "gpio_utils.h"
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#include "qm_isr.h"
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#include "clk.h"
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#include "soc.h"
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#include <power.h>
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struct gpio_qmsi_config {
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qm_gpio_t gpio;
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u8_t num_pins;
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};
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struct gpio_qmsi_runtime {
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sys_slist_t callbacks;
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u32_t pin_callbacks;
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#ifdef CONFIG_GPIO_QMSI_API_REENTRANCY
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struct k_sem sem;
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#endif /* CONFIG_GPIO_QMSI_API_REENTRANCY */
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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u32_t device_power_state;
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#endif
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};
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#ifdef CONFIG_GPIO_QMSI_API_REENTRANCY
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#define RP_GET(dev) (&((struct gpio_qmsi_runtime *)(dev->driver_data))->sem)
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#else
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#define RP_GET(context) (NULL)
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#endif /* CONFIG_GPIO_QMSI_API_REENTRANCY */
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static int gpio_qmsi_init(struct device *dev);
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static void gpio_qmsi_set_power_state(struct device *dev, u32_t power_state)
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{
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struct gpio_qmsi_runtime *context = dev->driver_data;
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context->device_power_state = power_state;
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}
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static u32_t gpio_qmsi_get_power_state(struct device *dev)
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{
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struct gpio_qmsi_runtime *context = dev->driver_data;
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return context->device_power_state;
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}
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#else
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#define gpio_qmsi_set_power_state(...)
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#endif
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#ifdef CONFIG_GPIO_QMSI_0
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static const struct gpio_qmsi_config gpio_0_config = {
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.gpio = QM_GPIO_0,
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.num_pins = QM_NUM_GPIO_PINS,
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};
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static struct gpio_qmsi_runtime gpio_0_runtime;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static qm_gpio_context_t gpio_ctx;
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static int gpio_suspend_device(struct device *dev)
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{
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const struct gpio_qmsi_config *gpio_config = dev->config->config_info;
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qm_gpio_save_context(gpio_config->gpio, &gpio_ctx);
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gpio_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
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return 0;
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}
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static int gpio_resume_device_from_suspend(struct device *dev)
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{
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const struct gpio_qmsi_config *gpio_config = dev->config->config_info;
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qm_gpio_restore_context(gpio_config->gpio, &gpio_ctx);
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gpio_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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/*
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* Implements the driver control management functionality
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* the *context may include IN data or/and OUT data
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*/
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static int gpio_qmsi_device_ctrl(struct device *port, u32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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return gpio_suspend_device(port);
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} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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return gpio_resume_device_from_suspend(port);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((u32_t *)context) = gpio_qmsi_get_power_state(port);
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return 0;
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}
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return 0;
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}
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#endif
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DEVICE_DEFINE(gpio_0, CONFIG_GPIO_QMSI_0_NAME, &gpio_qmsi_init,
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gpio_qmsi_device_ctrl, &gpio_0_runtime, &gpio_0_config,
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POST_KERNEL, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL);
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#endif /* CONFIG_GPIO_QMSI_0 */
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#ifdef CONFIG_GPIO_QMSI_1
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static const struct gpio_qmsi_config gpio_aon_config = {
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.gpio = QM_AON_GPIO_0,
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.num_pins = QM_NUM_AON_GPIO_PINS,
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};
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static struct gpio_qmsi_runtime gpio_aon_runtime;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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/*
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* Implements the driver control management functionality
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* the *context may include IN data or/and OUT data
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*/
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static int gpio_aon_device_ctrl(struct device *port, u32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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u32_t device_pm_state = *(u32_t *)context;
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if (device_pm_state == DEVICE_PM_SUSPEND_STATE ||
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device_pm_state == DEVICE_PM_ACTIVE_STATE) {
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gpio_qmsi_set_power_state(port, device_pm_state);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((u32_t *)context) = gpio_qmsi_get_power_state(port);
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}
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return 0;
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}
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#endif
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DEVICE_DEFINE(gpio_aon, CONFIG_GPIO_QMSI_1_NAME, &gpio_qmsi_init,
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gpio_aon_device_ctrl, &gpio_aon_runtime, &gpio_aon_config,
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POST_KERNEL, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL);
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#endif /* CONFIG_GPIO_QMSI_1 */
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static void gpio_qmsi_callback(void *data, u32_t status)
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{
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struct device *port = data;
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struct gpio_qmsi_runtime *context = port->driver_data;
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const u32_t enabled_mask = context->pin_callbacks & status;
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if (enabled_mask) {
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_gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
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}
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}
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static void qmsi_write_bit(u32_t *target, u8_t bit, u8_t value)
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{
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if (value) {
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sys_set_bit((uintptr_t) target, bit);
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} else {
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sys_clear_bit((uintptr_t) target, bit);
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}
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}
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static inline void qmsi_pin_config(struct device *port, u32_t pin, int flags)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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qm_gpio_port_config_t cfg = { 0 };
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cfg.direction = QM_GPIO[gpio]->gpio_swporta_ddr;
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cfg.int_en = QM_GPIO[gpio]->gpio_inten;
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cfg.int_type = QM_GPIO[gpio]->gpio_inttype_level;
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cfg.int_polarity = QM_GPIO[gpio]->gpio_int_polarity;
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cfg.int_debounce = QM_GPIO[gpio]->gpio_debounce;
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cfg.int_bothedge = QM_GPIO[gpio]->gpio_int_bothedge;
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cfg.callback = gpio_qmsi_callback;
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cfg.callback_data = port;
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qmsi_write_bit(&cfg.direction, pin, (flags & GPIO_DIR_MASK));
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if (flags & GPIO_INT) {
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qmsi_write_bit(&cfg.int_type, pin, (flags & GPIO_INT_EDGE));
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qmsi_write_bit(&cfg.int_polarity, pin,
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(flags & GPIO_INT_ACTIVE_HIGH));
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qmsi_write_bit(&cfg.int_debounce, pin,
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(flags & GPIO_INT_DEBOUNCE));
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qmsi_write_bit(&cfg.int_bothedge, pin,
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(flags & GPIO_INT_DOUBLE_EDGE));
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qmsi_write_bit(&cfg.int_en, pin, 1);
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} else {
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qmsi_write_bit(&cfg.int_en, pin, 0);
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}
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_take(RP_GET(port), K_FOREVER);
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}
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qm_gpio_set_config(gpio, &cfg);
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_give(RP_GET(port));
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}
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}
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static inline void qmsi_port_config(struct device *port, int flags)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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u8_t num_pins = gpio_config->num_pins;
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int i;
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for (i = 0; i < num_pins; i++) {
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qmsi_pin_config(port, i, flags);
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}
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}
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static inline int gpio_qmsi_config(struct device *port,
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int access_op, u32_t pin, int flags)
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{
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/* If the pin/port is set to receive interrupts, make sure the pin
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is an input */
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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return -EINVAL;
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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qmsi_pin_config(port, pin, flags);
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} else {
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qmsi_port_config(port, flags);
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}
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return 0;
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}
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static inline int gpio_qmsi_write(struct device *port,
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int access_op, u32_t pin, u32_t value)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_take(RP_GET(port), K_FOREVER);
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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qm_gpio_set_pin(gpio, pin);
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} else {
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qm_gpio_clear_pin(gpio, pin);
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}
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} else {
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qm_gpio_write_port(gpio, value);
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}
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_give(RP_GET(port));
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}
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return 0;
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}
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static inline int gpio_qmsi_read(struct device *port,
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int access_op, u32_t pin, u32_t *value)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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qm_gpio_state_t state;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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qm_gpio_read_pin(gpio, pin, &state);
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*value = state;
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} else {
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qm_gpio_read_port(gpio, (u32_t *const) value);
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}
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return 0;
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}
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static inline int gpio_qmsi_manage_callback(struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_qmsi_runtime *context = port->driver_data;
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_gpio_manage_callback(&context->callbacks, callback, set);
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return 0;
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}
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static inline int gpio_qmsi_enable_callback(struct device *port,
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int access_op, u32_t pin)
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{
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struct gpio_qmsi_runtime *context = port->driver_data;
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_take(RP_GET(port), K_FOREVER);
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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context->pin_callbacks |= BIT(pin);
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} else {
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context->pin_callbacks = 0xffffffff;
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}
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_give(RP_GET(port));
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}
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return 0;
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}
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static inline int gpio_qmsi_disable_callback(struct device *port,
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int access_op, u32_t pin)
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{
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struct gpio_qmsi_runtime *context = port->driver_data;
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_take(RP_GET(port), K_FOREVER);
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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context->pin_callbacks &= ~BIT(pin);
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} else {
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context->pin_callbacks = 0;
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}
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_give(RP_GET(port));
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}
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return 0;
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}
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static u32_t gpio_qmsi_get_pending_int(struct device *dev)
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{
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const struct gpio_qmsi_config *gpio_config = dev->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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return QM_GPIO[gpio]->gpio_intstatus;
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}
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static const struct gpio_driver_api api_funcs = {
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.config = gpio_qmsi_config,
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.write = gpio_qmsi_write,
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.read = gpio_qmsi_read,
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.manage_callback = gpio_qmsi_manage_callback,
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.enable_callback = gpio_qmsi_enable_callback,
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.disable_callback = gpio_qmsi_disable_callback,
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.get_pending_int = gpio_qmsi_get_pending_int,
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};
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static int gpio_qmsi_init(struct device *port)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
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k_sem_init(RP_GET(port), 1, UINT_MAX);
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}
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switch (gpio_config->gpio) {
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case QM_GPIO_0:
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clk_periph_enable(CLK_PERIPH_GPIO_REGISTER |
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CLK_PERIPH_GPIO_INTERRUPT |
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CLK_PERIPH_GPIO_DB |
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CLK_PERIPH_CLK);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_GPIO_0_INT),
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CONFIG_GPIO_QMSI_0_IRQ_PRI, qm_gpio_0_isr, 0,
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IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_GPIO_0_INT));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->gpio_0_int_mask);
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break;
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#ifdef CONFIG_GPIO_QMSI_1
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case QM_AON_GPIO_0:
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_AON_GPIO_0_INT),
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CONFIG_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_0_isr,
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0, IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_AON_GPIO_0_INT));
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QM_IR_UNMASK_INTERRUPTS(
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QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask);
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break;
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#endif /* CONFIG_GPIO_QMSI_1 */
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default:
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return -EIO;
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}
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gpio_qmsi_set_power_state(port, DEVICE_PM_ACTIVE_STATE);
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port->driver_api = &api_funcs;
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return 0;
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}
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