mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-03 01:51:56 +00:00
9413c8ba4d
Following migration of stm32f1xx series clock control driver to STM32Cube LL API, cleanup stm32 code base in order to take into account that this is the only clock driver available for stm32 family. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
273 lines
6.2 KiB
C
273 lines
6.2 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <soc.h>
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#include <gpio.h>
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#include <clock_control/stm32_clock_control.h>
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#include <pinmux/stm32/pinmux_stm32.h>
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#include <pinmux.h>
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#include <misc/util.h>
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#include <interrupt_controller/exti_stm32.h>
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#include "gpio_stm32.h"
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#include "gpio_utils.h"
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/**
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* @brief Common GPIO driver for STM32 MCUs. Each SoC must implement a
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* SoC specific integration glue
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*/
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/**
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* @brief EXTI interrupt callback
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*/
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static void gpio_stm32_isr(int line, void *arg)
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{
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struct device *dev = arg;
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struct gpio_stm32_data *data = dev->driver_data;
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if (BIT(line) & data->cb_pins) {
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_gpio_fire_callbacks(&data->cb, dev, BIT(line));
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}
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}
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/**
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* @brief Configure pin or port
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*/
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static int gpio_stm32_config(struct device *dev, int access_op,
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u32_t pin, int flags)
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{
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const struct gpio_stm32_config *cfg = dev->config->config_info;
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int pincfg;
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int map_res;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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/* figure out if we can map the requested GPIO
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* configuration
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*/
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map_res = stm32_gpio_flags_to_conf(flags, &pincfg);
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if (map_res) {
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return map_res;
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}
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if (stm32_gpio_configure(cfg->base, pin, pincfg, 0)) {
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return -EIO;
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}
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if (flags & GPIO_INT) {
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stm32_exti_set_callback(pin, gpio_stm32_isr, dev);
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stm32_gpio_enable_int(cfg->port, pin);
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if (flags & GPIO_INT_EDGE) {
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int edge = 0;
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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edge = STM32_EXTI_TRIG_RISING |
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STM32_EXTI_TRIG_FALLING;
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} else if (flags & GPIO_INT_ACTIVE_HIGH) {
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edge = STM32_EXTI_TRIG_RISING;
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} else {
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edge = STM32_EXTI_TRIG_FALLING;
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}
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stm32_exti_trigger(pin, edge);
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}
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stm32_exti_enable(pin);
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}
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return 0;
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}
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/**
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* @brief Set the pin or port output
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*/
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static int gpio_stm32_write(struct device *dev, int access_op,
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u32_t pin, u32_t value)
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{
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const struct gpio_stm32_config *cfg = dev->config->config_info;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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return stm32_gpio_set(cfg->base, pin, value);
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}
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/**
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* @brief Read the pin or port status
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*/
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static int gpio_stm32_read(struct device *dev, int access_op,
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u32_t pin, u32_t *value)
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{
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const struct gpio_stm32_config *cfg = dev->config->config_info;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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*value = stm32_gpio_get(cfg->base, pin);
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return 0;
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}
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static int gpio_stm32_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_stm32_data *data = dev->driver_data;
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_gpio_manage_callback(&data->cb, callback, set);
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return 0;
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}
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static int gpio_stm32_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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struct gpio_stm32_data *data = dev->driver_data;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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data->cb_pins |= BIT(pin);
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return 0;
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}
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static int gpio_stm32_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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struct gpio_stm32_data *data = dev->driver_data;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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data->cb_pins &= ~BIT(pin);
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return 0;
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}
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static const struct gpio_driver_api gpio_stm32_driver = {
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.config = gpio_stm32_config,
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.write = gpio_stm32_write,
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.read = gpio_stm32_read,
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.manage_callback = gpio_stm32_manage_callback,
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.enable_callback = gpio_stm32_enable_callback,
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.disable_callback = gpio_stm32_disable_callback,
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};
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/**
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* @brief Initialize GPIO port
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*
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* Perform basic initialization of a GPIO port. The code will
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* enable the clock for corresponding peripheral.
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*
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* @param dev GPIO device struct
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*
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* @return 0
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*/
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static int gpio_stm32_init(struct device *device)
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{
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const struct gpio_stm32_config *cfg = device->config->config_info;
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/* enable clock for subsystem */
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struct device *clk =
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device_get_binding(STM32_CLOCK_CONTROL_NAME);
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken);
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return 0;
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}
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#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __cenr, __bus) \
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static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
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.base = (u32_t *)__base_addr, \
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.port = __port, \
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.pclken = { .bus = __bus, .enr = __cenr } \
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}; \
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static struct gpio_stm32_data gpio_stm32_data_## __suffix; \
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DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
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__name, \
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gpio_stm32_init, \
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&gpio_stm32_data_## __suffix, \
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&gpio_stm32_cfg_## __suffix, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&gpio_stm32_driver);
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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/* On STM32F1 series, AFIO should be clocked to access GPIOs */
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#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \
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GPIO_DEVICE_INIT("GPIO" #__SUFFIX, __suffix, \
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GPIO##__SUFFIX##_BASE, STM32_PORT##__SUFFIX, \
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LL_APB2_GRP1_PERIPH_AFIO | \
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STM32_PERIPH_GPIO##__SUFFIX, \
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STM32_CLOCK_BUS_GPIO)
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#else
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#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \
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GPIO_DEVICE_INIT("GPIO" #__SUFFIX, __suffix, \
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GPIO##__SUFFIX##_BASE, STM32_PORT##__SUFFIX, \
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STM32_PERIPH_GPIO##__SUFFIX, \
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STM32_CLOCK_BUS_GPIO)
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#endif /* CONFIG_SOC_SERIES_STM32F1X */
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#ifdef CONFIG_GPIO_STM32_PORTA
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GPIO_DEVICE_INIT_STM32(a, A);
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#endif /* CONFIG_GPIO_STM32_PORTA */
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#ifdef CONFIG_GPIO_STM32_PORTB
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GPIO_DEVICE_INIT_STM32(b, B);
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#endif /* CONFIG_GPIO_STM32_PORTB */
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#ifdef CONFIG_GPIO_STM32_PORTC
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GPIO_DEVICE_INIT_STM32(c, C);
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#endif /* CONFIG_GPIO_STM32_PORTC */
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#ifdef CONFIG_GPIO_STM32_PORTD
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GPIO_DEVICE_INIT_STM32(d, D);
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#endif /* CONFIG_GPIO_STM32_PORTD */
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#ifdef CONFIG_GPIO_STM32_PORTE
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GPIO_DEVICE_INIT_STM32(e, E);
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#endif /* CONFIG_GPIO_STM32_PORTE */
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#ifdef CONFIG_GPIO_STM32_PORTF
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GPIO_DEVICE_INIT_STM32(f, F);
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#endif /* CONFIG_GPIO_STM32_PORTF */
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#ifdef CONFIG_GPIO_STM32_PORTG
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GPIO_DEVICE_INIT_STM32(g, G);
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#endif /* CONFIG_GPIO_STM32_PORTG */
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#ifdef CONFIG_GPIO_STM32_PORTH
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GPIO_DEVICE_INIT_STM32(h, H);
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#endif /* CONFIG_GPIO_STM32_PORTH */
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#ifdef CONFIG_GPIO_STM32_PORTI
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GPIO_DEVICE_INIT_STM32(i, I);
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#endif /* CONFIG_GPIO_STM32_PORTI */
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#ifdef CONFIG_GPIO_STM32_PORTJ
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GPIO_DEVICE_INIT_STM32(j, J);
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#endif /* CONFIG_GPIO_STM32_PORTJ */
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#ifdef CONFIG_GPIO_STM32_PORTK
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GPIO_DEVICE_INIT_STM32(k, K);
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#endif /* CONFIG_GPIO_STM32_PORTK */
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