Kumar Gala 95f78bcacf interrupt: Convert RISC-V plic to use multi-level irq support ... Utilize the multi-level irq infrastructure and replace custom handling for PLIC on riscv-privilege SoCs. The old code offset IRQs in drivers and various places with RISCV_MAX_GENERIC_IRQ. Instead utilize Zephyr's encoded IRQ and replace offsets in drivers with the IRQ define from DTS. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>		2019-09-10 07:34:57 -05:00
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arc
arm	linker: place debug header section for CC3235SF	2019-09-10 10:22:30 +03:00
common
nios2
posix
riscv	interrupt: Convert RISC-V plic to use multi-level irq support	2019-09-10 07:34:57 -05:00
x86
x86_64
xtensa
cpu.h
syscall.h