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https://github.com/zephyrproject-rtos/zephyr
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07160fa153
SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
143 lines
3.5 KiB
ArmAsm
143 lines
3.5 KiB
ArmAsm
/*
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* Copyright (c) 2019-2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <offsets_short.h>
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#include <arch/sparc/sparc.h>
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GTEXT(z_sparc_arch_switch)
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GTEXT(z_sparc_context_switch)
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GTEXT(z_thread_entry_wrapper)
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/* In this implementation, switch_handle is the thread itself. */
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SECTION_FUNC(TEXT, z_sparc_arch_switch)
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ba z_sparc_context_switch
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sub %o1, ___thread_t_switch_handle_OFFSET, %o1
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/*
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* This is a leaf function, so only out registers
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* can be used without saving their context first.
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*
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* o0: new thread to restore
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* o1: old thread to save
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*/
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SECTION_FUNC(TEXT, z_sparc_context_switch)
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mov %y, %o4
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st %o4, [%o1 + _thread_offset_to_y]
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std %l0, [%o1 + _thread_offset_to_l0_and_l1]
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std %l2, [%o1 + _thread_offset_to_l2]
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std %l4, [%o1 + _thread_offset_to_l4]
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std %l6, [%o1 + _thread_offset_to_l6]
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std %i0, [%o1 + _thread_offset_to_i0]
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std %i2, [%o1 + _thread_offset_to_i2]
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std %i4, [%o1 + _thread_offset_to_i4]
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std %i6, [%o1 + _thread_offset_to_i6]
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std %o6, [%o1 + _thread_offset_to_o6]
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rd %psr, %o4
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st %o4, [%o1 + _thread_offset_to_psr]
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and %o4, PSR_CWP, %g3 /* %g3 = CWP */
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andn %o4, PSR_ET, %g1 /* %g1 = psr with traps disabled */
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wr %g1, %psr /* disable traps */
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nop
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nop
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nop
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rd %wim, %g2 /* %g2 = wim */
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mov 1, %g4
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sll %g4, %g3, %g4 /* %g4 = wim mask for CW invalid */
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.Lsave_frame_loop:
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sll %g4, 1, %g5 /* rotate wim left by 1 */
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srl %g4, (CONFIG_SPARC_NWIN-1), %g4
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or %g4, %g5, %g4 /* %g4 = wim if we do one restore */
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/* if restore would not underflow, continue */
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andcc %g4, %g2, %g0 /* window to flush? */
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bnz .Ldone_flushing /* continue */
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nop
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restore /* go one window back */
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/* essentially the same as window overflow */
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/* sp still points to task stack */
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std %l0, [%sp + 0x00]
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std %l2, [%sp + 0x08]
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std %l4, [%sp + 0x10]
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std %l6, [%sp + 0x18]
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std %i0, [%sp + 0x20]
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std %i2, [%sp + 0x28]
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std %i4, [%sp + 0x30]
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std %i6, [%sp + 0x38]
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ba .Lsave_frame_loop
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nop
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.Ldone_flushing:
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/*
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* "wrpsr" is a delayed write instruction so wait three instructions
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* after the write before using non-global registers or instructions
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* affecting the CWP.
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*/
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wr %g1, %psr /* restore cwp */
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nop
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nop
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nop
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add %g3, 1, %g2 /* calculate desired wim */
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cmp %g2, (CONFIG_SPARC_NWIN-1) /* check if wim is in range */
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bg,a .Lwim_overflow
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mov 0, %g2
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.Lwim_overflow:
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mov 1, %g4
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sll %g4, %g2, %g4 /* %g4 = new wim */
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wr %g4, %wim
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nop
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nop
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nop
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ldd [%o0 + _thread_offset_to_y], %o4
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mov %o4, %y
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/* restore local registers */
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ldd [%o0 + _thread_offset_to_l0_and_l1], %l0
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ldd [%o0 + _thread_offset_to_l2], %l2
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ldd [%o0 + _thread_offset_to_l4], %l4
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ldd [%o0 + _thread_offset_to_l6], %l6
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/* restore input registers */
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ldd [%o0 + _thread_offset_to_i0], %i0
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ldd [%o0 + _thread_offset_to_i2], %i2
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ldd [%o0 + _thread_offset_to_i4], %i4
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ldd [%o0 + _thread_offset_to_i6], %i6
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/* restore output registers */
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ldd [%o0 + _thread_offset_to_o6], %o6
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ld [%o0 + _thread_offset_to_psr], %g1 /* %g1 = new thread psr */
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andn %g1, PSR_CWP, %g1 /* psr without cwp */
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or %g1, %g3, %g1 /* psr with new cwp */
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wr %g1, %psr /* restore status register and ET */
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nop
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nop
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nop
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/* jump into thread */
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jmp %o7 + 8
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nop
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SECTION_FUNC(TEXT, z_thread_entry_wrapper)
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mov %g0, %o7
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ld [%sp + 0x40], %o0
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ld [%sp + 0x44], %o1
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ld [%sp + 0x48], %o2
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ld [%sp + 0x4C], %o3
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call z_thread_entry
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nop
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