mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-03 14:21:56 +00:00
6422e1a36b
Updates the imx gpio driver and all associated boards to use new device tree compatible gpio configuration flags. Implements new port get/set/clear/toggle and pin_interrupt_configure functions recently added to the gpio api. Assumes the gpio api layer handles translating logical flags to physical flags. Tested with: - samples/basic/blinky - samples/basic/button - tests/drivers/gpio/gpio_api_1pin - tests/drivers/gpio/gpio_basic_api On boards: - udoo_neo_full_m4 Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
517 lines
13 KiB
C
517 lines
13 KiB
C
/*
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* Copyright (c) 2018-2019, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <soc.h>
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#include <sys/util.h>
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#include <gpio_imx.h>
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#include "gpio_utils.h"
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struct imx_gpio_config {
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GPIO_Type *base;
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};
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struct imx_gpio_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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/* pin callback routine enable flags, by pin number */
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u32_t pin_callback_enables;
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};
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static int imx_gpio_configure(struct device *port, int access_op, u32_t pin,
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int flags)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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GPIO_Type *base = config->base;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_SINGLE_ENDED
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| GPIO_PULL_UP
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| GPIO_PULL_DOWN)) != 0U) {
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return -ENOTSUP;
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}
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/* Disable interrupts for pin */
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GPIO_SetPinIntMode(base, pin, false);
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GPIO_SetIntEdgeSelect(base, pin, false);
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if ((flags & GPIO_OUTPUT) != 0U) {
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/* Set output pin initial value */
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if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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GPIO_WritePinOutput(base, pin, gpioPinClear);
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} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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GPIO_WritePinOutput(base, pin, gpioPinSet);
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}
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/* Set pin as output */
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WRITE_BIT(base->GDIR, pin, 1U);
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} else {
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/* Set pin as input */
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WRITE_BIT(base->GDIR, pin, 0U);
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}
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return 0;
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}
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static int imx_gpio_write(struct device *port,
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int access_op, u32_t pin, u32_t value)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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GPIO_WritePinOutput(config->base, pin,
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(gpio_pin_action_t)value);
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} else { /* GPIO_ACCESS_BY_PORT */
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GPIO_WritePortOutput(config->base, value);
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}
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return 0;
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}
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static int imx_gpio_read(struct device *port,
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int access_op, u32_t pin, u32_t *value)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = GPIO_ReadPinInput(config->base, pin);
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} else { /* GPIO_ACCESS_BY_PORT */
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*value = GPIO_ReadPortInput(config->base);
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}
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return 0;
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}
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static int imx_gpio_port_get_raw(struct device *port, u32_t *value)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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GPIO_Type *base = config->base;
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*value = GPIO_ReadPortInput(base);
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return 0;
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}
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static int imx_gpio_port_set_masked_raw(struct device *port,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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GPIO_Type *base = config->base;
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GPIO_WritePortOutput(base,
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(GPIO_ReadPortInput(base) & ~mask) | (value & mask));
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return 0;
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}
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static int imx_gpio_port_set_bits_raw(struct device *port,
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gpio_port_pins_t pins)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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GPIO_Type *base = config->base;
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GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) | pins);
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return 0;
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}
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static int imx_gpio_port_clear_bits_raw(struct device *port,
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gpio_port_pins_t pins)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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GPIO_Type *base = config->base;
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GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) & ~pins);
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return 0;
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}
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static int imx_gpio_port_toggle_bits(struct device *port, gpio_port_pins_t pins)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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GPIO_Type *base = config->base;
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GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) ^ pins);
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return 0;
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}
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static int imx_gpio_pin_interrupt_configure(struct device *port,
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unsigned int pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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struct imx_gpio_data *data = port->driver_data;
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GPIO_Type *base = config->base;
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volatile u32_t *icr_reg;
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unsigned int key;
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u32_t icr_val;
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u8_t shift;
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if (((base->GDIR & BIT(pin)) != 0U)
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&& (mode != GPIO_INT_MODE_DISABLED)) {
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/* Interrupt on output pin not supported */
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return -ENOTSUP;
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}
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if ((mode == GPIO_INT_MODE_EDGE) && (trig == GPIO_INT_TRIG_LOW)) {
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icr_val = 3U;
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} else if ((mode == GPIO_INT_MODE_EDGE) &&
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(trig == GPIO_INT_TRIG_HIGH)) {
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icr_val = 2U;
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} else if ((mode == GPIO_INT_MODE_LEVEL) &&
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(trig == GPIO_INT_TRIG_HIGH)) {
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icr_val = 1U;
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} else {
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icr_val = 0U;
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}
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if (pin < 16U) {
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shift = 2U * pin;
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icr_reg = &(base->ICR1);
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} else if (pin < 32U) {
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shift = 2U * (pin - 16U);
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icr_reg = &(base->ICR2);
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} else {
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return -EINVAL;
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}
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key = irq_lock();
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*icr_reg = (*icr_reg & ~(3U << shift)) | (icr_val << shift);
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WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH);
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WRITE_BIT(base->ISR, pin, mode != GPIO_INT_MODE_DISABLED);
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WRITE_BIT(base->IMR, pin, mode != GPIO_INT_MODE_DISABLED);
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WRITE_BIT(data->pin_callback_enables, pin,
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mode != GPIO_INT_MODE_DISABLED);
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irq_unlock(key);
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return 0;
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}
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static int imx_gpio_manage_callback(struct device *port,
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struct gpio_callback *cb, bool set)
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{
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struct imx_gpio_data *data = port->driver_data;
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return gpio_manage_callback(&data->callbacks, cb, set);
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}
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static int imx_gpio_enable_callback(struct device *port, int access_op,
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u32_t pin)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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struct imx_gpio_data *data = port->driver_data;
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u32_t i;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables |= BIT(pin);
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GPIO_SetPinIntMode(config->base, pin, true);
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} else {
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data->pin_callback_enables = 0xFFFFFFFFU;
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for (i = 0U; i < 32U; i++) {
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GPIO_SetPinIntMode(config->base, i, true);
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}
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}
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return 0;
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}
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static int imx_gpio_disable_callback(struct device *port, int access_op,
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u32_t pin)
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{
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const struct imx_gpio_config *config = port->config->config_info;
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struct imx_gpio_data *data = port->driver_data;
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u32_t i;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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GPIO_SetPinIntMode(config->base, pin, false);
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data->pin_callback_enables &= ~BIT(pin);
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} else {
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for (i = 0U; i < 32U; i++) {
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GPIO_SetPinIntMode(config->base, i, false);
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}
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data->pin_callback_enables = 0U;
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}
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return 0;
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}
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static void imx_gpio_port_isr(void *arg)
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{
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struct device *port = (struct device *)arg;
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const struct imx_gpio_config *config = port->config->config_info;
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struct imx_gpio_data *data = port->driver_data;
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u32_t enabled_int;
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enabled_int = config->base->ISR & data->pin_callback_enables;
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config->base->ISR = enabled_int;
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gpio_fire_callbacks(&data->callbacks, port, enabled_int);
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}
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static const struct gpio_driver_api imx_gpio_driver_api = {
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.config = imx_gpio_configure,
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.write = imx_gpio_write,
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.read = imx_gpio_read,
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.port_get_raw = imx_gpio_port_get_raw,
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.port_set_masked_raw = imx_gpio_port_set_masked_raw,
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.port_set_bits_raw = imx_gpio_port_set_bits_raw,
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.port_clear_bits_raw = imx_gpio_port_clear_bits_raw,
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.port_toggle_bits = imx_gpio_port_toggle_bits,
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.pin_interrupt_configure = imx_gpio_pin_interrupt_configure,
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.manage_callback = imx_gpio_manage_callback,
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.enable_callback = imx_gpio_enable_callback,
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.disable_callback = imx_gpio_disable_callback,
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};
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#ifdef CONFIG_GPIO_IMX_PORT_1
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static int imx_gpio_1_init(struct device *port);
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static const struct imx_gpio_config imx_gpio_1_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_1_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_1_data;
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DEVICE_AND_API_INIT(imx_gpio_1, DT_GPIO_IMX_PORT_1_NAME,
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imx_gpio_1_init,
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&imx_gpio_1_data, &imx_gpio_1_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_1_init(struct device *port)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_0,
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DT_GPIO_IMX_PORT_1_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0);
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irq_enable(DT_GPIO_IMX_PORT_1_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_1,
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DT_GPIO_IMX_PORT_1_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0);
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irq_enable(DT_GPIO_IMX_PORT_1_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_1 */
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#ifdef CONFIG_GPIO_IMX_PORT_2
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static int imx_gpio_2_init(struct device *port);
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static const struct imx_gpio_config imx_gpio_2_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_2_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_2_data;
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DEVICE_AND_API_INIT(imx_gpio_2, DT_GPIO_IMX_PORT_2_NAME,
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imx_gpio_2_init,
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&imx_gpio_2_data, &imx_gpio_2_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_2_init(struct device *port)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_0,
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DT_GPIO_IMX_PORT_2_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0);
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irq_enable(DT_GPIO_IMX_PORT_2_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_1,
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DT_GPIO_IMX_PORT_2_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0);
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irq_enable(DT_GPIO_IMX_PORT_2_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_2 */
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#ifdef CONFIG_GPIO_IMX_PORT_3
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static int imx_gpio_3_init(struct device *port);
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static const struct imx_gpio_config imx_gpio_3_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_3_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_3_data;
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DEVICE_AND_API_INIT(imx_gpio_3, DT_GPIO_IMX_PORT_3_NAME,
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imx_gpio_3_init,
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&imx_gpio_3_data, &imx_gpio_3_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_3_init(struct device *port)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_0,
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DT_GPIO_IMX_PORT_3_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0);
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irq_enable(DT_GPIO_IMX_PORT_3_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_1,
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DT_GPIO_IMX_PORT_3_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0);
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irq_enable(DT_GPIO_IMX_PORT_3_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_3 */
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#ifdef CONFIG_GPIO_IMX_PORT_4
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static int imx_gpio_4_init(struct device *port);
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static const struct imx_gpio_config imx_gpio_4_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_4_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_4_data;
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DEVICE_AND_API_INIT(imx_gpio_4, DT_GPIO_IMX_PORT_4_NAME,
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imx_gpio_4_init,
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&imx_gpio_4_data, &imx_gpio_4_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_4_init(struct device *port)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_0,
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DT_GPIO_IMX_PORT_4_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0);
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irq_enable(DT_GPIO_IMX_PORT_4_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_1,
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DT_GPIO_IMX_PORT_4_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0);
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irq_enable(DT_GPIO_IMX_PORT_4_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_4 */
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#ifdef CONFIG_GPIO_IMX_PORT_5
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static int imx_gpio_5_init(struct device *port);
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static const struct imx_gpio_config imx_gpio_5_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_5_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_5_data;
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DEVICE_AND_API_INIT(imx_gpio_5, DT_GPIO_IMX_PORT_5_NAME,
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imx_gpio_5_init,
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&imx_gpio_5_data, &imx_gpio_5_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_5_init(struct device *port)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_0,
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DT_GPIO_IMX_PORT_5_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0);
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irq_enable(DT_GPIO_IMX_PORT_5_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_1,
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DT_GPIO_IMX_PORT_5_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0);
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irq_enable(DT_GPIO_IMX_PORT_5_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_5 */
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#ifdef CONFIG_GPIO_IMX_PORT_6
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static int imx_gpio_6_init(struct device *port);
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static const struct imx_gpio_config imx_gpio_6_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_6_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_6_data;
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DEVICE_AND_API_INIT(imx_gpio_6, DT_GPIO_IMX_PORT_6_NAME,
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imx_gpio_6_init,
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&imx_gpio_6_data, &imx_gpio_6_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_6_init(struct device *port)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_0,
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DT_GPIO_IMX_PORT_6_IRQ_0_PRI,
|
|
imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0);
|
|
|
|
irq_enable(DT_GPIO_IMX_PORT_6_IRQ_0);
|
|
|
|
IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_1,
|
|
DT_GPIO_IMX_PORT_6_IRQ_1_PRI,
|
|
imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0);
|
|
|
|
irq_enable(DT_GPIO_IMX_PORT_6_IRQ_1);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_GPIO_IMX_PORT_6 */
|
|
|
|
#ifdef CONFIG_GPIO_IMX_PORT_7
|
|
static int imx_gpio_7_init(struct device *port);
|
|
|
|
static const struct imx_gpio_config imx_gpio_7_config = {
|
|
.base = (GPIO_Type *)DT_GPIO_IMX_PORT_7_BASE_ADDRESS,
|
|
};
|
|
|
|
static struct imx_gpio_data imx_gpio_7_data;
|
|
|
|
DEVICE_AND_API_INIT(imx_gpio_7, DT_GPIO_IMX_PORT_7_NAME,
|
|
imx_gpio_7_init,
|
|
&imx_gpio_7_data, &imx_gpio_7_config,
|
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
&imx_gpio_driver_api);
|
|
|
|
static int imx_gpio_7_init(struct device *port)
|
|
{
|
|
IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_0,
|
|
DT_GPIO_IMX_PORT_7_IRQ_0_PRI,
|
|
imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0);
|
|
|
|
irq_enable(DT_GPIO_IMX_PORT_7_IRQ_0);
|
|
|
|
IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_1,
|
|
DT_GPIO_IMX_PORT_7_IRQ_1_PRI,
|
|
imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0);
|
|
|
|
irq_enable(DT_GPIO_IMX_PORT_7_IRQ_1);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_GPIO_IMX_PORT_7 */
|