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35cfe113d2
Macros and enums are included for supporting pin configuration settings. Entries to the dts_fixup were also included in order to configure port level settings. Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
24 lines
553 B
C
24 lines
553 B
C
/*
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Microchip XEC MCU family General Purpose Input Output (GPIO) defines.
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*
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*/
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#ifndef _MICROCHIP_MEC_SOC_GPIO_H_
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#define _MICROCHIP_MEC_SOC_GPIO_H_
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#define MCHP_GPIO_000_036 0
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#define MCHP_GPIO_040_076 1
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#define MCHP_GPIO_100_136 2
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#define MCHP_GPIO_140_176 3
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#define MCHP_GPIO_200_236 4
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#define MCHP_GPIO_240_276 5
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#define MCHP_GPIO_MAX_PORT 6
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#define MCHP_NUM_GPIO_PORTS 6
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#endif /* _MICROCHIP_MEC_SOC_GPIO_H_ */
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