mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-07 15:32:36 +00:00
7e0eed9235
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
152 lines
3.7 KiB
C
152 lines
3.7 KiB
C
/*
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* Copyright (c) 2020 Libre Solar Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_dac
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#include <errno.h>
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#include <drivers/dac.h>
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#include <device.h>
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#include <kernel.h>
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#include <init.h>
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#include <soc.h>
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#define LOG_LEVEL CONFIG_DAC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(dac_stm32);
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#include <drivers/clock_control/stm32_clock_control.h>
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/* some low-end MCUs have DAC with only one channel */
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#ifdef LL_DAC_CHANNEL_2
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#define STM32_CHANNEL_COUNT 2
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#else
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#define STM32_CHANNEL_COUNT 1
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#endif
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/* first channel always named 1 */
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#define STM32_FIRST_CHANNEL 1
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#define CHAN(n) LL_DAC_CHANNEL_##n
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static const u32_t table_channels[] = {
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CHAN(1),
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#ifdef LL_DAC_CHANNEL_2
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CHAN(2),
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#endif
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};
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/* Read-only driver configuration */
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struct dac_stm32_cfg {
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DAC_TypeDef *base;
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struct stm32_pclken pclken;
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};
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/* Runtime driver data */
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struct dac_stm32_data {
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u8_t channel_count;
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u8_t resolution;
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};
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static int dac_stm32_write_value(struct device *dev,
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u8_t channel, u32_t value)
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{
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struct dac_stm32_data *data = dev->driver_data;
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const struct dac_stm32_cfg *cfg = dev->config_info;
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if (channel - STM32_FIRST_CHANNEL >= data->channel_count ||
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channel < STM32_FIRST_CHANNEL) {
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LOG_ERR("Channel %d is not valid", channel);
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return -EINVAL;
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}
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if (data->resolution == 8) {
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LL_DAC_ConvertData8RightAligned(cfg->base,
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table_channels[channel - STM32_FIRST_CHANNEL], value);
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} else if (data->resolution == 12) {
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LL_DAC_ConvertData12RightAligned(cfg->base,
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table_channels[channel - STM32_FIRST_CHANNEL], value);
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}
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return 0;
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}
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static int dac_stm32_channel_setup(struct device *dev,
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const struct dac_channel_cfg *channel_cfg)
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{
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struct dac_stm32_data *data = dev->driver_data;
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const struct dac_stm32_cfg *cfg = dev->config_info;
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if ((channel_cfg->channel_id - STM32_FIRST_CHANNEL >=
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data->channel_count) ||
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(channel_cfg->channel_id < STM32_FIRST_CHANNEL)) {
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LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
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return -EINVAL;
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}
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if ((channel_cfg->resolution == 8) ||
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(channel_cfg->resolution == 12)) {
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data->resolution = channel_cfg->resolution;
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} else {
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LOG_ERR("Resolution not supported");
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return -ENOTSUP;
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}
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/* enable output buffer by default */
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LL_DAC_SetOutputBuffer(cfg->base,
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table_channels[channel_cfg->channel_id - STM32_FIRST_CHANNEL],
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LL_DAC_OUTPUT_BUFFER_ENABLE);
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LL_DAC_Enable(cfg->base,
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table_channels[channel_cfg->channel_id - STM32_FIRST_CHANNEL]);
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LOG_DBG("Channel setup succeeded!");
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return 0;
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}
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static int dac_stm32_init(struct device *dev)
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{
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const struct dac_stm32_cfg *cfg = dev->config_info;
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/* enable clock for subsystem */
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struct device *clk =
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device_get_binding(STM32_CLOCK_CONTROL_NAME);
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if (clock_control_on(clk,
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(clock_control_subsys_t *) &cfg->pclken) != 0) {
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return -EIO;
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}
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return 0;
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}
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static const struct dac_driver_api api_stm32_driver_api = {
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.channel_setup = dac_stm32_channel_setup,
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.write_value = dac_stm32_write_value
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};
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#define STM32_DAC_INIT(index) \
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\
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static const struct dac_stm32_cfg dac_stm32_cfg_##index = { \
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.base = (DAC_TypeDef *)DT_INST_REG_ADDR(index), \
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.pclken = { \
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.enr = DT_INST_CLOCKS_CELL(index, bits), \
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.bus = DT_INST_CLOCKS_CELL(index, bus), \
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}, \
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}; \
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static struct dac_stm32_data dac_stm32_data_##index = { \
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.channel_count = STM32_CHANNEL_COUNT \
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}; \
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\
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DEVICE_AND_API_INIT(dac_##index, DT_INST_LABEL(index), \
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&dac_stm32_init, &dac_stm32_data_##index, \
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&dac_stm32_cfg_##index, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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&api_stm32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(STM32_DAC_INIT)
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