mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-09 09:42:43 +00:00
745dd6f931
Page table management for x86 is being revised such that there will not in many cases be a pristine, master set of page tables. Instead, when mapping memory, use unused PTE bits to store the original RW, US, and XD settings when the mapping was made. This will allow memory domains to alter page tables while still being able to restore the original mapping permissions. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
503 lines
17 KiB
Python
Executable File
503 lines
17 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# Copyright (c) 2020 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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"""Create the kernel's page tables for x86 CPUs.
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For additional detail on paging and x86 memory management, please
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consult the IA Architecture SW Developer Manual, volume 3a, chapter 4.
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This script produces the initial page tables installed into the CPU
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at early boot. These pages will have an identity mapping at
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CONFIG_SRAM_BASE_ADDRESS of size CONFIG_SRAM_SIZE. The script takes
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the 'zephyr_prebuilt.elf' as input to obtain region sizes, certain
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memory addresses, and configuration values.
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If CONFIG_SRAM_REGION_PERMISSIONS is not enabled, all RAM will be
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mapped with the Present and Write bits set. The linker scripts shouldn't
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add page alignment padding between sections.
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If CONFIG_SRAM_REGION_PERMISSIONS is enabled, the access permissions
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vary:
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- By default, the Present, Write, and Execute Disable bits are
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set.
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- The _image_text region will have Present and User bits set
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- The _image_rodata region will have Present, User, and Execute
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Disable bits set
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- On x86_64, the _locore region will have Present set and
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the _lorodata region will have Present and Execute Disable set.
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Because the set of page tables are linked together by physical address,
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we must know a priori the physical address of each table. The linker
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script must define a z_x86_pagetables_start symbol where the page
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tables will be placed, and this memory address must not shift between
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prebuilt and final ELF builds. This script will not work on systems
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where the physical load address of the kernel is unknown at build time.
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64-bit systems will always build IA-32e page tables. 32-bit systems
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build PAE page tables if CONFIG_X86_PAE is set, otherwise standard
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32-bit page tables are built.
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The kernel will expect to find the top-level structure of the produced
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page tables at the physical address corresponding to the symbol
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z_x86_kernel_ptables. The linker script will need to set that symbol
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to the end of the binary produced by this script, minus the size of the
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top-level paging structure as it is written out last.
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"""
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import sys
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import array
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import argparse
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import os
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import struct
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import elftools
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from distutils.version import LooseVersion
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from elftools.elf.elffile import ELFFile
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from elftools.elf.sections import SymbolTableSection
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if LooseVersion(elftools.__version__) < LooseVersion('0.24'):
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sys.exit("pyelftools is out of date, need version 0.24 or later")
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def bit(pos):
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return 1 << pos
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# Page table entry flags
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FLAG_P = bit(0)
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FLAG_RW = bit(1)
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FLAG_US = bit(2)
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FLAG_G = bit(8)
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FLAG_XD = bit(63)
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FLAG_IGNORED0 = bit(9)
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FLAG_IGNORED1 = bit(10)
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FLAG_IGNORED2 = bit(11)
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ENTRY_RW = FLAG_RW | FLAG_IGNORED0
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ENTRY_US = FLAG_US | FLAG_IGNORED1
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ENTRY_XD = FLAG_XD | FLAG_IGNORED2
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def debug(text):
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if not args.verbose:
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return
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sys.stdout.write(os.path.basename(sys.argv[0]) + ": " + text + "\n")
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def error(text):
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sys.exit(os.path.basename(sys.argv[0]) + ": " + text)
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def align_check(base, size):
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if (base % 4096) != 0:
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error("unaligned base address %x" % base)
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if (size % 4096) != 0:
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error("Unaligned region size %d for base %x" % (size, base))
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def dump_flags(flags):
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ret = ""
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if flags & FLAG_P:
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ret += "P "
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if flags & FLAG_RW:
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ret += "RW "
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if flags & FLAG_US:
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ret += "US "
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if flags & FLAG_G:
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ret += "G "
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if flags & FLAG_XD:
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ret += "XD "
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return ret.strip()
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# Hard-coded flags for intermediate paging levels. Permissive, we only control
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# access or set caching properties at leaf levels.
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INT_FLAGS = FLAG_P | FLAG_RW | FLAG_US
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class MMUTable(object):
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"""Represents a particular table in a set of page tables, at any level"""
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def __init__(self):
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self.entries = array.array(self.type_code,
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[0 for i in range(self.num_entries)])
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def get_binary(self):
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"""Return a bytearray representation of this table"""
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# Always little-endian
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ctype = "<" + self.type_code
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entry_size = struct.calcsize(ctype)
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ret = bytearray(entry_size * self.num_entries)
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for i in range(self.num_entries):
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struct.pack_into(ctype, ret, entry_size * i, self.entries[i])
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return ret
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@property
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def supported_flags(self):
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"""Class property indicating what flag bits are supported"""
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raise NotImplementedError()
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@property
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def addr_shift(self):
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"""Class property for how much to shift virtual addresses to obtain
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the appropriate index in the table for it"""
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raise NotImplementedError()
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@property
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def addr_mask(self):
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"""Mask to apply to an individual entry to get the physical address
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mapping"""
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raise NotImplementedError()
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@property
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def type_code(self):
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"""Struct packing letter code for table entries. Either I for
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32-bit entries, or Q for PAE/IA-32e"""
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raise NotImplementedError()
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@property
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def num_entries(self):
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"""Number of entries in the table. Varies by table type and paging
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mode"""
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raise NotImplementedError()
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def entry_index(self, virt_addr):
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"""Get the index of the entry in this table that corresponds to the
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provided virtual address"""
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return (virt_addr >> self.addr_shift) & (self.num_entries - 1)
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def has_entry(self, virt_addr):
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"""Indicate whether an entry is present in this table for the provided
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virtual address"""
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index = self.entry_index(virt_addr)
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return (self.entries[index] & FLAG_P) != 0
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def lookup(self, virt_addr):
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"""Look up the physical mapping for a virtual address.
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If this is a leaf table, this is the physical address mapping. If not,
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this is the physical address of the next level table"""
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index = self.entry_index(virt_addr)
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return self.entries[index] & self.addr_mask
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def map(self, virt_addr, phys_addr, entry_flags):
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"""For the table entry corresponding to the provided virtual address,
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set the corresponding physical entry in the table. Unsupported flags
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will be filtered out.
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If this is a leaf table, this is the physical address mapping. If not,
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this is the physical address of the next level table"""
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index = self.entry_index(virt_addr)
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self.entries[index] = ((phys_addr & self.addr_mask) |
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(entry_flags & self.supported_flags))
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def set_perms(self, virt_addr, entry_flags):
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""""For the table entry corresponding to the provided virtual address,
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update just the flags, leaving the physical mapping alone.
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Unsupported flags will be filtered out."""
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index = self.entry_index(virt_addr)
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self.entries[index] = ((self.entries[index] & self.addr_mask) |
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(entry_flags & self.supported_flags))
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# Specific supported table types
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class Pml4(MMUTable):
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"""Page mapping level 4 for IA-32e"""
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addr_shift = 39
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addr_mask = 0x7FFFFFFFFFFFF000
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type_code = 'Q'
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num_entries = 512
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supported_flags = INT_FLAGS
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class Pdpt(MMUTable):
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"""Page directory pointer table for IA-32e"""
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addr_shift = 30
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addr_mask = 0x7FFFFFFFFFFFF000
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type_code = 'Q'
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num_entries = 512
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supported_flags = INT_FLAGS
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class PdptPAE(Pdpt):
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"""Page directory pointer table for PAE"""
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num_entries = 4
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class Pd(MMUTable):
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"""Page directory for 32-bit"""
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addr_shift = 22
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addr_mask = 0xFFFFF000
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type_code = 'I'
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num_entries = 1024
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supported_flags = INT_FLAGS
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class PdXd(Pd):
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"""Page directory for either PAE or IA-32e"""
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addr_shift = 21
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addr_mask = 0x7FFFFFFFFFFFF000
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num_entries = 512
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type_code = 'Q'
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class Pt(MMUTable):
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"""Page table for 32-bit"""
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addr_shift = 12
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addr_mask = 0xFFFFF000
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type_code = 'I'
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num_entries = 1024
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supported_flags = (FLAG_P | FLAG_RW | FLAG_US | FLAG_G |
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FLAG_IGNORED0 | FLAG_IGNORED1)
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class PtXd(Pt):
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"""Page table for either PAE or IA-32e"""
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addr_mask = 0x07FFFFFFFFFFF000
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type_code = 'Q'
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num_entries = 512
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supported_flags = (FLAG_P | FLAG_RW | FLAG_US | FLAG_G | FLAG_XD |
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FLAG_IGNORED0 | FLAG_IGNORED1 | FLAG_IGNORED2)
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class PtableSet(object):
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"""Represents a complete set of page tables for any paging mode"""
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def __init__(self, pages_start):
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"""Instantiate a set of page tables which will be located in the
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image starting at the provided physical memory location"""
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self.page_pos = pages_start
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self.toplevel = self.levels[0]()
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debug("%s starting at physical address 0x%x" %
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(self.__class__.__name__, pages_start))
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# Database of page table pages. Maps physical memory address to
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# MMUTable objects, excluding the top-level table which is tracked
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# separately. Starts out empty as we haven't mapped anything and
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# the top-level table is tracked separately.
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self.tables = {}
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def get_new_mmutable_addr(self):
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"""If we need to instantiate a new MMUTable, return a physical
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address location for it"""
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ret = self.page_pos
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self.page_pos += 4096
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return ret
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@property
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def levels(self):
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"""Class hierarchy of paging levels, with the first entry being
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the toplevel table class, and the last entry always being
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some kind of leaf page table class (Pt or PtXd)"""
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raise NotImplementedError()
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def map_page(self, virt_addr, phys_addr, flags):
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"""Map a virtual address to a physical address in the page tables,
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with provided access flags"""
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table = self.toplevel
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# Create and link up intermediate tables if necessary
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for depth in range(1, len(self.levels)):
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# Create child table if needed
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if not table.has_entry(virt_addr):
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new_table_addr = self.get_new_mmutable_addr()
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new_table = self.levels[depth]()
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debug("new %s at physical addr 0x%x"
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% (self.levels[depth].__name__, new_table_addr))
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self.tables[new_table_addr] = new_table
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table.map(virt_addr, new_table_addr, INT_FLAGS)
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table = new_table
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else:
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table = self.tables[table.lookup(virt_addr)]
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# Set up entry in leaf page table
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table.map(virt_addr, phys_addr, flags)
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def map(self, phys_base, size, flags):
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"""Identity map an address range in the page tables, with provided
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access flags.
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"""
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debug("Identity-mapping 0x%x (%d): %s" %
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(phys_base, size, dump_flags(flags)))
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align_check(phys_base, size)
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for addr in range(phys_base, phys_base + size, 4096):
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if addr == 0:
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# Never map the NULL page
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continue
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self.map_page(addr, addr, flags)
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def set_region_perms(self, name, flags):
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"""Set access permissions for a named region that is already mapped
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The bounds of the region will be looked up in the symbol table
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with _start and _size suffixes. The physical address mapping
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is unchanged and this will not disturb any double-mapping."""
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# Doesn't matter if this is a virtual address, we have a
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# either dual mapping or it's the same as physical
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base = syms[name + "_start"]
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size = syms[name + "_size"]
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debug("change flags for %s at 0x%x (%d): %s" %
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(name, base, size, dump_flags(flags)))
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align_check(base, size)
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try:
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for addr in range(base, base + size, 4096):
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# Never map the NULL page
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if addr == 0:
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continue
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table = self.toplevel
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for _ in range(1, len(self.levels)):
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table = self.tables[table.lookup(addr)]
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table.set_perms(addr, flags)
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except KeyError:
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error("no mapping for %s region 0x%x (size 0x%x)" %
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(name, base, size))
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def write_output(self, filename):
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"""Write the page tables to the output file in binary format"""
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with open(filename, "wb") as fp:
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for addr in sorted(self.tables):
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mmu_table = self.tables[addr]
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fp.write(mmu_table.get_binary())
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# We always have the top-level table be last. This is because
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# in PAE, the top-level PDPT has only 4 entries and is not a
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# full page in size. We do not put it in the tables dictionary
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# and treat it as a special case.
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debug("top-level %s at physical addr 0x%x" %
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(self.toplevel.__class__.__name__,
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self.get_new_mmutable_addr()))
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fp.write(self.toplevel.get_binary())
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# Paging mode classes, we'll use one depending on configuration
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class Ptables32bit(PtableSet):
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levels = [Pd, Pt]
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class PtablesPAE(PtableSet):
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levels = [PdptPAE, PdXd, PtXd]
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class PtablesIA32e(PtableSet):
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levels = [Pml4, Pdpt, PdXd, PtXd]
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def parse_args():
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global args
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parser = argparse.ArgumentParser(
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description=__doc__,
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formatter_class=argparse.RawDescriptionHelpFormatter)
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parser.add_argument("-k", "--kernel", required=True,
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help="path to prebuilt kernel ELF binary")
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parser.add_argument("-o", "--output", required=True,
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help="output file")
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parser.add_argument("-v", "--verbose", action="store_true",
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help="Print extra debugging information")
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args = parser.parse_args()
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if "VERBOSE" in os.environ:
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args.verbose = True
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def get_symbols(obj):
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for section in obj.iter_sections():
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if isinstance(section, SymbolTableSection):
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return {sym.name: sym.entry.st_value
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for sym in section.iter_symbols()}
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raise LookupError("Could not find symbol table")
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def isdef(sym_name):
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return sym_name in syms
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def main():
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global syms
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parse_args()
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with open(args.kernel, "rb") as fp:
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kernel = ELFFile(fp)
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syms = get_symbols(kernel)
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if isdef("CONFIG_X86_64"):
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pclass = PtablesIA32e
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elif isdef("CONFIG_X86_PAE"):
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pclass = PtablesPAE
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else:
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pclass = Ptables32bit
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debug("building %s" % pclass.__name__)
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ram_base = syms["CONFIG_SRAM_BASE_ADDRESS"]
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ram_size = syms["CONFIG_SRAM_SIZE"] * 1024
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ptables_phys = syms["z_x86_pagetables_start"]
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debug("Base addresses: physical 0x%x size %d" % (ram_base, ram_size))
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is_perm_regions = isdef("CONFIG_SRAM_REGION_PERMISSIONS")
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if is_perm_regions:
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# Don't allow execution by default for any pages. We'll adjust this
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# in later calls to pt.set_region_perms()
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map_flags = FLAG_P | ENTRY_XD
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else:
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map_flags = FLAG_P
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pt = pclass(ptables_phys)
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pt.map(ram_base, ram_size, map_flags | ENTRY_RW)
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if isdef("CONFIG_XIP"):
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# Additionally identity-map all ROM as read-only
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pt.map(syms["CONFIG_FLASH_BASE_ADDRESS"],
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syms["CONFIG_FLASH_SIZE"] * 1024, map_flags)
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# Adjust mapped region permissions if configured
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if is_perm_regions:
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# Need to accomplish the following things:
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# - Text regions need the XD flag cleared and RW flag removed
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# if not built with gdbstub support
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# - Rodata regions need the RW flag cleared
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# - User mode needs access as we currently do not separate application
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# text/rodata from kernel text/rodata
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if isdef("CONFIG_GDBSTUB"):
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pt.set_region_perms("_image_text", FLAG_P | ENTRY_US | ENTRY_RW)
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else:
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pt.set_region_perms("_image_text", FLAG_P | ENTRY_US)
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pt.set_region_perms("_image_rodata", FLAG_P | ENTRY_US | ENTRY_XD)
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if isdef("CONFIG_COVERAGE_GCOV") and isdef("CONFIG_USERSPACE"):
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# If GCOV is enabled, user mode must be able to write to its
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# common data area
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pt.set_region_perms("__gcov_bss",
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FLAG_P | ENTRY_RW | ENTRY_US | ENTRY_XD)
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if isdef("CONFIG_X86_64"):
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# Set appropriate permissions for locore areas much like we did
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# with the main text/rodata regions
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if isdef("CONFIG_X86_KPTI"):
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# Set the User bit for the read-only locore/lorodata areas.
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# This ensures they get mapped into the User page tables if
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# KPTI is turned on. There is no sensitive data in them, and
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# they contain text/data needed to take an exception or
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# interrupt.
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flag_user = ENTRY_US
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else:
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flag_user = 0
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pt.set_region_perms("_locore", FLAG_P | flag_user)
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pt.set_region_perms("_lorodata", FLAG_P | ENTRY_XD | flag_user)
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pt.write_output(args.output)
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if __name__ == "__main__":
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main()
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