mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 14:22:32 +00:00
aec9a8c4be
Before introducing the code for ARM64 (AArch64) we need to relocate the current ARM code to a new AArch32 sub-directory. For now we can assume that no code is shared between ARM and ARM64. There are no functional changes. The code is moved to the new location and the file paths are fixed to reflect this change. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
48 lines
880 B
C
48 lines
880 B
C
/*
|
|
* Copyright (c) 2016 RnDity Sp. z o.o.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
/**
|
|
* @file
|
|
* @brief System/hardware module for STM32F3 processor
|
|
*/
|
|
|
|
#include <device.h>
|
|
#include <init.h>
|
|
#include <arch/cpu.h>
|
|
#include <arch/arm/aarch32/cortex_m/cmsis.h>
|
|
|
|
/**
|
|
* @brief Perform basic hardware initialization at boot.
|
|
*
|
|
* This needs to be run from the very beginning.
|
|
* So the init priority has to be 0 (zero).
|
|
*
|
|
* @return 0
|
|
*/
|
|
static int stm32f3_init(struct device *arg)
|
|
{
|
|
u32_t key;
|
|
|
|
ARG_UNUSED(arg);
|
|
|
|
key = irq_lock();
|
|
|
|
/* Install default handler that simply resets the CPU
|
|
* if configured in the kernel, NOP otherwise
|
|
*/
|
|
NMI_INIT();
|
|
|
|
irq_unlock(key);
|
|
|
|
/* Update CMSIS SystemCoreClock variable (HCLK) */
|
|
/* At reset, system core clock is set to 8 MHz from HSI */
|
|
SystemCoreClock = 8000000;
|
|
|
|
return 0;
|
|
}
|
|
|
|
SYS_INIT(stm32f3_init, PRE_KERNEL_1, 0);
|