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This adds initial Cortex-R support for interrupts and context switching. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
33 lines
619 B
C
33 lines
619 B
C
/*
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* Copyright (c) 2018 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _CORTEX_R_CPU_H
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#define _CORTEX_R_CPU_H
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#define MODE_USR 0x10
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#define MODE_FIQ 0x11
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define MODE_ABT 0x17
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#define MODE_UDF 0x1b
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#define MODE_SYS 0x1f
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#define MODE_MASK 0x1f
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#define A_BIT (1 << 8)
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#define I_BIT (1 << 7)
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#define F_BIT (1 << 6)
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#define T_BIT (1 << 5)
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#define HIVECS (1 << 13)
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#define RET_FROM_SVC 0
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#define RET_FROM_IRQ 1
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#define __ISB() __asm__ volatile ("isb sy" : : : "memory")
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#define __DMB() __asm__ volatile ("dmb sy" : : : "memory")
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#endif
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