mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-15 13:21:56 +00:00
aff81e7513
Add Voltage-Divider node for VBUS to board level device tree Signed-off-by: Sam Hurst <sbh1187@gmail.com>
164 lines
3.4 KiB
Plaintext
164 lines
3.4 KiB
Plaintext
/*
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* Copyright 2021 The Chromium OS Authors
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <st/g0/stm32g081Xb.dtsi>
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#include <st/g0/stm32g081rbtx-pinctrl.dtsi>
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/ {
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model = "STM32G081B EVAL board";
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compatible = "st,stm32g081-eval";
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chosen {
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zephyr,console = &usart3;
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zephyr,shell-uart = &usart3;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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};
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leds {
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compatible = "gpio-leds";
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led_1: led1 {
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gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>;
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label = "LED1";
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};
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led_2: led2 {
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gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>;
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label = "LED2";
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};
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led_3: led3 {
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gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
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label = "LED3";
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};
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led_4: led4 {
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gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
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label = "LED4";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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joy_sel: button0 {
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label = "JOY_SEL";
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gpios = <&gpioa 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
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};
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joy_left: button1 {
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label = "JOY_LEFT";
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gpios = <&gpioc 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
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};
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joy_down: button2 {
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label = "JOY_DOWN";
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gpios = <&gpioc 3 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
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};
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joy_right: button3 {
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label = "JOY_RIGHT";
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gpios = <&gpioc 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
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};
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joy_up: button4 {
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label = "JOY_UP";
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gpios = <&gpioc 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
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};
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};
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discharge_vbus2_config {
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compatible = "gpio-leds";
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/*
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* Pin B14 is used to control VBUS Discharge for Port2
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*/
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discharge_vbus2 {
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gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
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label = "DISCHARGE_VBUS2";
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};
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};
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aliases {
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led0 = &led_1;
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led1 = &led_2;
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led2 = &led_3;
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led3 = &led_4;
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sw0 = &joy_sel;
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sw1 = &joy_left;
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sw2 = &joy_down;
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sw3 = &joy_right;
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sw4 = &joy_up;
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};
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vbus {
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compatible = "voltage-divider";
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io-channels = <&adc1 3>;
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output-ohms = <49900>;
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full-ohms = <(330000 + 49900)>;
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};
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};
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&clk_hsi {
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status = "okay";
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};
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&pll {
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div-m = <1>;
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mul-n = <8>;
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div-p = <2>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(64)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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};
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&usart3 {
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pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>;
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pinctrl-names = "default";
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current-speed = <115200>;
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status = "okay";
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};
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&adc1 {
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pinctrl-0 = <&adc1_in3_pa3>;
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pinctrl-names = "default";
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status = "okay";
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};
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&ucpd2 {
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status = "okay";
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/*
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* UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
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* a prescaler who's output feeds the 'half-bit' divider which is used
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* to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
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* designed to work in freq ranges of 6 <--> 18 MHz, however recommended
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* range is 9 <--> 18 MHz.
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*
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* +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
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* HSI ---->| /psc |--------->| /hbit |--------------->| trans_cnt |
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* +-------+ +-------+ | +-----------+
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* | +-----------+
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* +----------->| ifrgap_cnt|
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* +-----------+
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* Requirements:
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* 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
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* 2. tTransitionWindow - 12 to 20 uSec
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* 3. tInterframGap - uSec
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*
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* hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
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* tTransitionWindow = 1.687 uS * 8 = 13.5 uS
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* tInterFrameGap = 1.687 uS * 17 = 28.68 uS
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*/
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psc-ucpdclk = <1>;
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hbitclkdiv = <27>;
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};
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&iwdg {
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status = "okay";
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};
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