mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-13 12:25:22 +00:00
e3f2fa4f89
This interrupt controller is a designware IP that combines several sources of interrupt into one line that is then routed to the parent controller. This implementation supports only the regular irqs with no support for priority filtering and vectored interrupts. Firqs are also not supported. Change-Id: I8bdf6f8df4632b6d7e8a3ba9a77116771d034a48 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _DW_ICTL_H_
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#define _DW_ICTL_H_
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void (*dw_ictl_config_irq_t)(struct device *port);
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struct dw_ictl_config {
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u32_t irq_num;
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u32_t numirqs;
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u32_t isr_table_offset;
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dw_ictl_config_irq_t config_func;
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};
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struct dw_ictl_runtime {
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u32_t base_addr;
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};
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struct dw_ictl_registers {
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u32_t irq_inten_l; /* offset 00 */
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u32_t irq_inten_h; /* offset 04 */
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u32_t irq_intmask_l; /* offset 08 */
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u32_t irq_intmask_h; /* offset 0C */
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u32_t irq_intforce_l; /* offset 10 */
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u32_t irq_intforce_h; /* offset 14 */
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u32_t irq_rawstatus_l; /* offset 18 */
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u32_t irq_rawstatus_h; /* offset 1c */
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u32_t irq_status_l; /* offset 20 */
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u32_t irq_status_h; /* offset 24 */
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u32_t irq_maskstatus_l; /* offset 28 */
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u32_t irq_maskstatus_h; /* offset 2c */
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u32_t irq_finalstatus_l; /* offset 30 */
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u32_t irq_finalstatus_h; /* offset 34 */
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u32_t irq_vector; /* offset 38 */
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u32_t Reserved1; /* offset 3c */
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u32_t irq_vector_0; /* offset 40 */
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u32_t Reserved2; /* offset 44 */
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u32_t irq_vector_1; /* offset 48 */
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u32_t Reserved3; /* offset 4c */
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u32_t irq_vector_2; /* offset 50 */
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u32_t Reserved4; /* offset 54 */
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u32_t irq_vector_3; /* offset 58 */
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u32_t Reserved5; /* offset 5c */
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u32_t irq_vector_4; /* offset 60 */
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u32_t Reserved6; /* offset 64 */
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u32_t irq_vector_5; /* offset 68 */
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u32_t Reserved7; /* offset 6c */
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u32_t irq_vector_6; /* offset 70 */
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u32_t Reserved8; /* offset 74 */
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u32_t irq_vector_7; /* offset 78 */
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u32_t Reserved9; /* offset 7c */
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u32_t irq_vector_8; /* offset 80 */
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u32_t Reserved10; /* offset 84 */
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u32_t irq_vector_9; /* offset 88 */
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u32_t Reserved11; /* offset 8c */
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u32_t irq_vector_10; /* offset 90 */
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u32_t Reserved12; /* offset 94 */
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u32_t irq_vector_11; /* offset 98 */
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u32_t Reserved13; /* offset 9c */
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u32_t irq_vector_12; /* offset a0 */
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u32_t Reserved14; /* offset a4 */
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u32_t irq_vector_13; /* offset a8 */
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u32_t Reserved15; /* offset ac */
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u32_t irq_vector_14; /* offset b0 */
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u32_t Reserved16; /* offset b4 */
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u32_t irq_vector_15; /* offset b8 */
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u32_t Reserved17; /* offset bc */
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u32_t fiq_inten; /* offset c0 */
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u32_t fiq_intmask; /* offset c4 */
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u32_t fiq_intforce; /* offset c8 */
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u32_t fiq_rawstatus; /* offset cc */
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u32_t fiq_status; /* offset d0 */
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u32_t fiq_finalstatus; /* offset d4 */
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u32_t irq_plevel; /* offset d8 */
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u32_t Reserved18; /* offset dc */
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u32_t APB_ICTL_COMP_VERSION; /* offset e0 */
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u32_t Reserved19; /* offset e4 */
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DW_ICTL_H_ */
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