mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-07 07:22:50 +00:00
32bb2395c2
Kernel timeouts have always been a 32 bit integer despite the existence of generation macros, and existing code has been inconsistent about using them. Upcoming commits are going to make the timeout arguments opaque, so fix things up to be rigorously correct. Changes include: + Adding a K_TIMEOUT_EQ() macro for code that needs to compare timeout values for equality (e.g. with K_FOREVER or K_NO_WAIT). + Adding a k_msleep() synonym for k_sleep() which can continue to take integral arguments as k_sleep() moves away to timeout arguments. + Pervasively using the K_MSEC(), K_SECONDS(), et. al. macros to generate timeout arguments. + Removing the usage of K_NO_WAIT as the final argument to K_THREAD_DEFINE(). This is just a count of milliseconds and we need to use a zero. This patch include no logic changes and should not affect generated code at all. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
369 lines
9.3 KiB
C
369 lines
9.3 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2017 BayLibre, SAS.
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* Copyright (c) 2019 Centaur Analytics, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT soc_nv_flash
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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#include <drivers/flash.h>
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#include <init.h>
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#include <soc.h>
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#include <logging/log.h>
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#include "flash_stm32.h"
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LOG_MODULE_REGISTER(flash_stm32, CONFIG_FLASH_LOG_LEVEL);
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/* STM32F0: maximum erase time of 40ms for a 2K sector */
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#if defined(CONFIG_SOC_SERIES_STM32F0X)
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#define STM32_FLASH_MAX_ERASE_TIME 40
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/* STM32F3: maximum erase time of 40ms for a 2K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32F1X)
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#define STM32_FLASH_MAX_ERASE_TIME 40
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/* STM32F3: maximum erase time of 40ms for a 2K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32F3X)
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#define STM32_FLASH_MAX_ERASE_TIME 40
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/* STM32F4: maximum erase time of 4s for a 128K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32F4X)
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#define STM32_FLASH_MAX_ERASE_TIME 4000
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/* STM32F7: maximum erase time of 4s for a 256K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32F7X)
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#define STM32_FLASH_MAX_ERASE_TIME 4000
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/* STM32L4: maximum erase time of 24.47ms for a 2K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32L4X)
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#define STM32_FLASH_MAX_ERASE_TIME 25
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/* STM32WB: maximum erase time of 24.5ms for a 4K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32WBX)
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#define STM32_FLASH_MAX_ERASE_TIME 25
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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/* STM32G0: maximum erase time of 40ms for a 2K sector */
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#define STM32_FLASH_MAX_ERASE_TIME 40
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/* STM32G4: maximum erase time of 24.47ms for a 2K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32G4X)
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#define STM32_FLASH_MAX_ERASE_TIME 25
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#endif
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/* Let's wait for double the max erase time to be sure that the operation is
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* completed.
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*/
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#define STM32_FLASH_TIMEOUT (2 * STM32_FLASH_MAX_ERASE_TIME)
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#define CFG_HW_FLASH_SEMID 2
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#if defined(CONFIG_MULTITHREADING)
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/*
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* This is named flash_stm32_sem_take instead of flash_stm32_lock (and
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* similarly for flash_stm32_sem_give) to avoid confusion with locking
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* actual flash pages.
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*/
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static inline void _flash_stm32_sem_take(struct device *dev)
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{
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
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}
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER);
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}
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static inline void _flash_stm32_sem_give(struct device *dev)
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{
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k_sem_give(&FLASH_STM32_PRIV(dev)->sem);
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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}
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#define flash_stm32_sem_init(dev) k_sem_init(&FLASH_STM32_PRIV(dev)->sem, 1, 1)
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#define flash_stm32_sem_take(dev) _flash_stm32_sem_take(dev)
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#define flash_stm32_sem_give(dev) _flash_stm32_sem_give(dev)
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#else
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#define flash_stm32_sem_init(dev)
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#define flash_stm32_sem_take(dev)
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#define flash_stm32_sem_give(dev)
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#endif
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#if !defined(CONFIG_SOC_SERIES_STM32WBX)
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static int flash_stm32_check_status(struct device *dev)
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{
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u32_t const error =
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#if defined(FLASH_FLAG_PGAERR)
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FLASH_FLAG_PGAERR |
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#endif
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#if defined(FLASH_FLAG_RDERR)
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FLASH_FLAG_RDERR |
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#endif
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#if defined(FLASH_FLAG_PGPERR)
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FLASH_FLAG_PGPERR |
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#endif
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#if defined(FLASH_FLAG_PGSERR)
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FLASH_FLAG_PGSERR |
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#endif
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#if defined(FLASH_FLAG_OPERR)
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FLASH_FLAG_OPERR |
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#endif
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#if defined(FLASH_FLAG_PGERR)
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FLASH_FLAG_PGERR |
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#endif
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FLASH_FLAG_WRPERR;
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if (FLASH_STM32_REGS(dev)->SR & error) {
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LOG_DBG("Status: 0x%08x", FLASH_STM32_REGS(dev)->SR & error);
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return -EIO;
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}
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return 0;
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}
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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int flash_stm32_wait_flash_idle(struct device *dev)
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{
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s64_t timeout_time = k_uptime_get() + STM32_FLASH_TIMEOUT;
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int rc;
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rc = flash_stm32_check_status(dev);
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if (rc < 0) {
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return -EIO;
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}
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#if defined(CONFIG_SOC_SERIES_STM32G0X)
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while ((FLASH_STM32_REGS(dev)->SR & FLASH_SR_BSY1)) {
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#else
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while ((FLASH_STM32_REGS(dev)->SR & FLASH_SR_BSY)) {
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#endif
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if (k_uptime_get() > timeout_time) {
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LOG_ERR("Timeout! val: %d", STM32_FLASH_TIMEOUT);
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return -EIO;
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}
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}
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return 0;
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}
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static void flash_stm32_flush_caches(struct device *dev,
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off_t offset, size_t len)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X)
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ARG_UNUSED(dev);
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ARG_UNUSED(offset);
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ARG_UNUSED(len);
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#elif defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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ARG_UNUSED(offset);
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ARG_UNUSED(len);
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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if (regs->ACR & FLASH_ACR_DCEN) {
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regs->ACR &= ~FLASH_ACR_DCEN;
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regs->ACR |= FLASH_ACR_DCRST;
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regs->ACR &= ~FLASH_ACR_DCRST;
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regs->ACR |= FLASH_ACR_DCEN;
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}
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#elif defined(CONFIG_SOC_SERIES_STM32F7X)
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SCB_InvalidateDCache_by_Addr((uint32_t *)(CONFIG_FLASH_BASE_ADDRESS
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+ offset), len);
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#endif
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}
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static int flash_stm32_read(struct device *dev, off_t offset, void *data,
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size_t len)
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{
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if (!flash_stm32_valid_range(dev, offset, len, false)) {
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LOG_ERR("Read range invalid. Offset: %ld, len: %zu",
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(long int) offset, len);
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return -EINVAL;
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}
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if (!len) {
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return 0;
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}
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LOG_DBG("Read offset: %ld, len: %zu", (long int) offset, len);
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memcpy(data, (u8_t *) CONFIG_FLASH_BASE_ADDRESS + offset, len);
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return 0;
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}
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static int flash_stm32_erase(struct device *dev, off_t offset, size_t len)
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{
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int rc;
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if (!flash_stm32_valid_range(dev, offset, len, true)) {
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LOG_ERR("Erase range invalid. Offset: %ld, len: %zu",
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(long int) offset, len);
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return -EINVAL;
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}
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if (!len) {
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return 0;
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}
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flash_stm32_sem_take(dev);
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LOG_DBG("Erase offset: %ld, len: %zu", (long int) offset, len);
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rc = flash_stm32_block_erase_loop(dev, offset, len);
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flash_stm32_flush_caches(dev, offset, len);
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flash_stm32_sem_give(dev);
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return rc;
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}
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static int flash_stm32_write(struct device *dev, off_t offset,
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const void *data, size_t len)
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{
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int rc;
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if (!flash_stm32_valid_range(dev, offset, len, true)) {
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LOG_ERR("Write range invalid. Offset: %ld, len: %zu",
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(long int) offset, len);
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return -EINVAL;
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}
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if (!len) {
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return 0;
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}
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flash_stm32_sem_take(dev);
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LOG_DBG("Write offset: %ld, len: %zu", (long int) offset, len);
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rc = flash_stm32_write_range(dev, offset, data, len);
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flash_stm32_sem_give(dev);
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return rc;
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}
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static int flash_stm32_write_protection(struct device *dev, bool enable)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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int rc = 0;
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flash_stm32_sem_take(dev);
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if (enable) {
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc) {
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flash_stm32_sem_give(dev);
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return rc;
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}
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regs->CR |= FLASH_CR_LOCK;
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LOG_DBG("Enable write protection");
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} else {
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if (regs->CR & FLASH_CR_LOCK) {
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regs->KEYR = FLASH_KEY1;
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regs->KEYR = FLASH_KEY2;
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}
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LOG_DBG("Disable write protection");
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}
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flash_stm32_sem_give(dev);
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return rc;
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}
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static struct flash_stm32_priv flash_data = {
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.regs = (FLASH_TypeDef *) DT_INST_REG_ADDR(0),
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_FLASH },
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#endif
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};
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static const struct flash_driver_api flash_stm32_api = {
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.write_protection = flash_stm32_write_protection,
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.erase = flash_stm32_erase,
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.write = flash_stm32_write,
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.read = flash_stm32_read,
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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.page_layout = flash_stm32_page_layout,
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#endif
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#if DT_INST_NODE_HAS_PROP(0, write_block_size)
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.write_block_size = DT_INST_PROP(0, write_block_size),
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#else
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#error Flash write block size not available
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/* Flash Write block size is extracted from device tree */
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/* as flash node property 'write-block-size' */
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#endif
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};
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static int stm32_flash_init(struct device *dev)
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{
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X)
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struct flash_stm32_priv *p = FLASH_STM32_PRIV(dev);
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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/*
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* On STM32F0, Flash interface clock source is always HSI,
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* so statically enable HSI here.
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*/
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X)
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LL_RCC_HSI_Enable();
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while (!LL_RCC_HSI_IsReady()) {
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}
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#endif
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/* enable clock */
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if (clock_control_on(clk, (clock_control_subsys_t *)&p->pclken) != 0) {
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LOG_ERR("Failed to enable clock");
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return -EIO;
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}
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#endif
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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flash_stm32_sem_init(dev);
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LOG_DBG("Flash initialized. BS: %zu",
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flash_stm32_api.write_block_size);
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#if ((CONFIG_FLASH_LOG_LEVEL >= LOG_LEVEL_DBG) && CONFIG_FLASH_PAGE_LAYOUT)
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const struct flash_pages_layout *layout;
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size_t layout_size;
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flash_stm32_page_layout(dev, &layout, &layout_size);
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for (size_t i = 0; i < layout_size; i++) {
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LOG_DBG("Block %zu: bs: %zu count: %zu", i,
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layout[i].pages_size, layout[i].pages_count);
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}
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#endif
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return flash_stm32_write_protection(dev, false);
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}
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DEVICE_AND_API_INIT(stm32_flash, DT_FLASH_DEV_NAME,
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stm32_flash_init, &flash_data, NULL, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_stm32_api);
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