mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-03 06:32:00 +00:00
ac81eb0eca
This commit removes the redundant definition of nRF GPIOTE register structure that is present in gpio_nrf5.c. The gpiote driver is adapted to use the register definitions directly from Nordic MDK header files. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
484 lines
13 KiB
C
484 lines
13 KiB
C
/*
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* Copyright (c) 2016-2018 Nordic Semiconductor ASA
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* Copyright (c) 2017 ARM Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file Driver for the Nordic Semiconductor nRF5X GPIO module.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <gpio.h>
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#include <soc.h>
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#include <sys_io.h>
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#include <nrf_gpiote.h>
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#include "nrf_common.h"
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#include "gpio_utils.h"
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#define GPIO_PIN_CNF_SENSE_Invalid 0x01
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/*@todo: move GPIOTE channel management to a separate module */
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/* Reserve channels below the base index */
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#define GPIOTE_CH_BASE CONFIG_GPIO_NRF5_GPIOTE_CHAN_BASE
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static u32_t gpiote_chan_mask = BIT_MASK(GPIOTE_CH_BASE);
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/** Configuration data */
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struct gpio_nrf5_config {
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/* GPIO module base address */
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u32_t gpio_base_addr;
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/* GPIO port */
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u8_t gpio_port;
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};
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struct gpio_nrf5_data {
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/* list of registered callbacks */
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sys_slist_t callbacks;
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/* pin callback routine enable flags, by pin number */
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u32_t pin_callback_enables;
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};
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/* convenience defines for GPIO */
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#define DEV_GPIO_CFG(dev) \
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((const struct gpio_nrf5_config * const)(dev)->config->config_info)
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#define DEV_GPIO_DATA(dev) \
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((struct gpio_nrf5_data * const)(dev)->driver_data)
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#define GPIO_STRUCT(dev) \
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((volatile NRF_GPIO_Type *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
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#define GPIO_PORT(dev) \
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(DEV_GPIO_CFG(dev)->gpio_port)
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#define GPIO_SENSE_DISABLE (GPIO_PIN_CNF_SENSE_Disabled << \
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GPIO_PIN_CNF_SENSE_Pos)
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#define GPIO_SENSE_LOW (GPIO_PIN_CNF_SENSE_Low << \
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GPIO_PIN_CNF_SENSE_Pos)
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#define GPIO_SENSE_HIGH (GPIO_PIN_CNF_SENSE_High << \
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GPIO_PIN_CNF_SENSE_Pos)
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#define GPIO_SENSE_INVALID (GPIO_PIN_CNF_SENSE_Invalid << \
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GPIO_PIN_CNF_SENSE_Pos)
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#define GPIO_PULL_DISABLE (GPIO_PIN_CNF_PULL_Disabled << \
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GPIO_PIN_CNF_PULL_Pos)
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#define GPIO_PULL_DOWN (GPIO_PIN_CNF_PULL_Pulldown << \
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GPIO_PIN_CNF_PULL_Pos)
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#define GPIO_PULL_UP (GPIO_PIN_CNF_PULL_Pullup << \
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GPIO_PIN_CNF_PULL_Pos)
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#define GPIO_INPUT_CONNECT (GPIO_PIN_CNF_INPUT_Connect << \
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GPIO_PIN_CNF_INPUT_Pos)
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#define GPIO_INPUT_DISCONNECT (GPIO_PIN_CNF_INPUT_Disconnect << \
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GPIO_PIN_CNF_INPUT_Pos)
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#define GPIO_DIR_INPUT (GPIO_PIN_CNF_DIR_Input << \
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GPIO_PIN_CNF_DIR_Pos)
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#define GPIO_DIR_OUTPUT (GPIO_PIN_CNF_DIR_Output << \
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GPIO_PIN_CNF_DIR_Pos)
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#define GPIO_DRIVE_S0S1 (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_H0S1 (GPIO_PIN_CNF_DRIVE_H0S1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_S0H1 (GPIO_PIN_CNF_DRIVE_S0H1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_H0H1 (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_D0S1 (GPIO_PIN_CNF_DRIVE_D0S1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_D0H1 (GPIO_PIN_CNF_DRIVE_D0H1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_S0D1 (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_H0D1 (GPIO_PIN_CNF_DRIVE_H0D1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIOTE_CFG_EVT (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos)
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#define GPIOTE_CFG_TASK (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos)
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#define GPIOTE_CFG_POL_L2H (GPIOTE_CONFIG_POLARITY_LoToHi << \
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GPIOTE_CONFIG_POLARITY_Pos)
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#define GPIOTE_CFG_POL_H2L (GPIOTE_CONFIG_POLARITY_HiToLo << \
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GPIOTE_CONFIG_POLARITY_Pos)
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#define GPIOTE_CFG_POL_TOGG (GPIOTE_CONFIG_POLARITY_Toggle << \
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GPIOTE_CONFIG_POLARITY_Pos)
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#if defined(CONFIG_GPIO_NRF5_P1)
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#define GPIOTE_CFG_PORT(port) ((port << GPIOTE_CONFIG_PORT_Pos) & \
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GPIOTE_CONFIG_PORT_Msk)
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#define GPIOTE_CFG_PORT_GET(config) ((config & GPIOTE_CONFIG_PORT_Msk) >> \
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GPIOTE_CONFIG_PORT_Pos)
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#else /* !CONFIG_GPIO_NRF5_P1 */
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#define GPIOTE_CFG_PORT(port) 0
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#define GPIOTE_CFG_PORT_GET(config) 0
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#endif /* !CONFIG_GPIO_NRF5_P1 */
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#define GPIOTE_CFG_PIN(pin) ((pin << GPIOTE_CONFIG_PSEL_Pos) & \
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GPIOTE_CONFIG_PSEL_Msk)
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#define GPIOTE_CFG_PIN_GET(config) ((config & GPIOTE_CONFIG_PSEL_Msk) >> \
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GPIOTE_CONFIG_PSEL_Pos)
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static int gpiote_find_channel(struct device *dev, u32_t pin, u32_t port)
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{
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volatile NRF_GPIOTE_Type *gpiote = (void *)NRF_GPIOTE_BASE;
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int i;
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for (i = GPIOTE_CH_BASE; i < GPIOTE_CH_NUM; i++) {
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if ((gpiote_chan_mask & BIT(i)) &&
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(GPIOTE_CFG_PIN_GET(gpiote->CONFIG[i]) == pin) &&
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(GPIOTE_CFG_PORT_GET(gpiote->CONFIG[i]) == port)) {
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return i;
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}
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}
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return -ENODEV;
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}
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/**
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* @brief Configure pin or port
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*/
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static int gpio_nrf5_config(struct device *dev,
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int access_op, u32_t pin, int flags)
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{
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/* Note D0D1 is not supported so we switch to S0S1. */
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static const u32_t drive_strength[4][4] = {
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{GPIO_DRIVE_S0S1, GPIO_DRIVE_S0H1, 0, GPIO_DRIVE_S0D1},
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{GPIO_DRIVE_H0S1, GPIO_DRIVE_H0H1, 0, GPIO_DRIVE_H0D1},
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{0, 0, 0, 0},
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{GPIO_DRIVE_D0S1, GPIO_DRIVE_D0H1, 0, GPIO_DRIVE_S0S1}
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};
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volatile NRF_GPIOTE_Type *gpiote = (void *)NRF_GPIOTE_BASE;
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volatile NRF_GPIO_Type *gpio = GPIO_STRUCT(dev);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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/* Check pull */
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u8_t pull = GPIO_PULL_DISABLE;
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int ds_low = (flags & GPIO_DS_LOW_MASK) >> GPIO_DS_LOW_POS;
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int ds_high = (flags & GPIO_DS_HIGH_MASK) >> GPIO_DS_HIGH_POS;
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unsigned int sense = (flags & GPIO_PIN_CNF_SENSE_Msk);
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__ASSERT_NO_MSG(ds_low != 2);
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__ASSERT_NO_MSG(ds_high != 2);
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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pull = GPIO_PULL_UP;
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} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
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pull = GPIO_PULL_DOWN;
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}
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if (sense == GPIO_SENSE_INVALID) {
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__ASSERT_NO_MSG(sense == GPIO_SENSE_INVALID);
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sense = GPIO_SENSE_DISABLE;
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}
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
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/* Set initial output value */
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if (pull == GPIO_PULL_UP) {
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gpio->OUTSET = BIT(pin);
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} else if (pull == GPIO_PULL_DOWN) {
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gpio->OUTCLR = BIT(pin);
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}
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/* Config as output */
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gpio->PIN_CNF[pin] = (GPIO_SENSE_DISABLE |
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drive_strength[ds_low][ds_high] |
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pull |
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GPIO_INPUT_DISCONNECT |
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GPIO_DIR_OUTPUT);
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} else {
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/* Config as input */
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gpio->PIN_CNF[pin] = (sense |
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drive_strength[ds_low][ds_high] |
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pull |
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GPIO_INPUT_CONNECT |
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GPIO_DIR_INPUT);
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}
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} else {
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return -ENOTSUP;
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}
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if (flags & GPIO_INT) {
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u32_t config = 0;
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u32_t port = GPIO_PORT(dev);
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/* check if already allocated to replace */
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int i = gpiote_find_channel(dev, pin, port);
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if (i < 0) {
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if (popcount(gpiote_chan_mask) == GPIOTE_CH_NUM) {
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return -EIO;
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}
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/* allocate a GPIOTE channel */
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i = find_lsb_set(~gpiote_chan_mask) - 1;
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gpiote_chan_mask |= BIT(i);
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}
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/* configure GPIOTE channel */
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if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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config |= GPIOTE_CFG_POL_TOGG;
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} else if (flags & GPIO_INT_ACTIVE_HIGH) {
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config |= GPIOTE_CFG_POL_L2H;
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} else {
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config |= GPIOTE_CFG_POL_H2L;
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}
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} else { /* GPIO_INT_LEVEL */
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/*@todo: use SENSE for this? */
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return -ENOTSUP;
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}
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config |= GPIOTE_CFG_EVT;
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config |= GPIOTE_CFG_PIN(pin);
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config |= GPIOTE_CFG_PORT(port);
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gpiote->CONFIG[i] = config;
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}
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return 0;
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}
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static int gpio_nrf5_read(struct device *dev,
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int access_op, u32_t pin, u32_t *value)
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{
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volatile NRF_GPIO_Type *gpio = GPIO_STRUCT(dev);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = (gpio->IN >> pin) & 0x1;
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} else {
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*value = gpio->IN;
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}
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return 0;
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}
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static int gpio_nrf5_write(struct device *dev,
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int access_op, u32_t pin, u32_t value)
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{
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volatile NRF_GPIO_Type *gpio = GPIO_STRUCT(dev);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) { /* 1 */
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gpio->OUTSET = BIT(pin);
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} else { /* 0 */
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gpio->OUTCLR = BIT(pin);
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}
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} else {
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gpio->OUT = value;
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}
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return 0;
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}
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static int gpio_nrf5_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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_gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static int gpio_nrf5_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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if (access_op == GPIO_ACCESS_BY_PIN) {
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volatile NRF_GPIOTE_Type *gpiote = (void *)NRF_GPIOTE_BASE;
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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int port = GPIO_PORT(dev);
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int i;
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i = gpiote_find_channel(dev, pin, port);
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if (i < 0) {
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return i;
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}
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data->pin_callback_enables |= BIT(pin);
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/* clear event before any interrupt triggers */
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gpiote->EVENTS_IN[i] = 0;
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/* enable interrupt for the GPIOTE channel */
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gpiote->INTENSET = BIT(i);
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_nrf5_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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if (access_op == GPIO_ACCESS_BY_PIN) {
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volatile NRF_GPIOTE_Type *gpiote = (void *)NRF_GPIOTE_BASE;
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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int port = GPIO_PORT(dev);
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int i;
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i = gpiote_find_channel(dev, pin, port);
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if (i < 0) {
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return i;
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}
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data->pin_callback_enables &= ~(BIT(pin));
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/* disable interrupt for the GPIOTE channel */
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gpiote->INTENCLR = BIT(i);
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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/* NOTE: forward declarations to use in ISR below */
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#if defined(CONFIG_GPIO_NRF5_P0)
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DEVICE_DECLARE(gpio_nrf5_P0);
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#endif /* CONFIG_GPIO_NRF5_P0 */
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#if defined(CONFIG_GPIO_NRF5_P1)
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DEVICE_DECLARE(gpio_nrf5_P1);
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#endif /* CONFIG_GPIO_NRF5_P1 */
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/**
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* @brief Handler for port interrupts
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* @param dev Pointer to device structure for driver instance
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*
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* @return N/A
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*/
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static void gpio_nrf5_port_isr(void *arg)
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{
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volatile NRF_GPIOTE_Type *gpiote = (void *)NRF_GPIOTE_BASE;
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struct gpio_nrf5_data *data;
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#if defined(CONFIG_GPIO_NRF5_P0)
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u32_t int_status_p0 = 0;
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#endif /* CONFIG_GPIO_NRF5_P0 */
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#if defined(CONFIG_GPIO_NRF5_P1)
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u32_t int_status_p1 = 0;
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#endif /* CONFIG_GPIO_NRF5_P1 */
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struct device *dev;
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u32_t enabled_int;
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int i;
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for (i = GPIOTE_CH_BASE; i < GPIOTE_CH_NUM; i++) {
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if (gpiote->EVENTS_IN[i]) {
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int port = GPIOTE_CFG_PORT_GET(gpiote->CONFIG[i]);
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int pin = GPIOTE_CFG_PIN_GET(gpiote->CONFIG[i]);
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gpiote->EVENTS_IN[i] = 0;
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switch (port) {
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#if defined(CONFIG_GPIO_NRF5_P0)
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case 0:
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int_status_p0 |= BIT(pin);
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break;
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#endif /* CONFIG_GPIO_NRF5_P0 */
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#if defined(CONFIG_GPIO_NRF5_P1)
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case 1:
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int_status_p1 |= BIT(pin);
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break;
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#endif /* CONFIG_GPIO_NRF5_P1 */
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default:
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/* NOTE: unknown port, ignore it */
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break;
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}
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}
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}
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#if defined(CONFIG_GPIO_NRF5_P0)
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dev = DEVICE_GET(gpio_nrf5_P0);
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data = DEV_GPIO_DATA(dev);
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enabled_int = int_status_p0 & data->pin_callback_enables;
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/* Call the registered callbacks */
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_gpio_fire_callbacks(&data->callbacks, (struct device *)dev,
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enabled_int);
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#endif /* CONFIG_GPIO_NRF5_P0 */
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#if defined(CONFIG_GPIO_NRF5_P1)
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dev = DEVICE_GET(gpio_nrf5_P1);
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data = DEV_GPIO_DATA(dev);
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enabled_int = int_status_p1 & data->pin_callback_enables;
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/* Call the registered callbacks */
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_gpio_fire_callbacks(&data->callbacks, (struct device *)dev,
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enabled_int);
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#endif /* CONFIG_GPIO_NRF5_P1 */
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}
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static const struct gpio_driver_api gpio_nrf5_drv_api_funcs = {
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.config = gpio_nrf5_config,
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.read = gpio_nrf5_read,
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.write = gpio_nrf5_write,
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.manage_callback = gpio_nrf5_manage_callback,
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.enable_callback = gpio_nrf5_enable_callback,
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.disable_callback = gpio_nrf5_disable_callback,
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};
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static int gpio_nrf5_init(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_GPIOTE_NRF5_IRQ, CONFIG_GPIOTE_NRF5_IRQ_PRI,
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gpio_nrf5_port_isr, NULL, 0);
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irq_enable(CONFIG_GPIOTE_NRF5_IRQ);
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return 0;
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}
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/* Enable GPIOTE Interrupt */
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void nrf_gpiote_interrupt_enable(uint32_t mask)
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{
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nrf_gpiote_int_enable(mask);
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}
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/* Disable GPIOTE Interrupt */
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void nrf_gpiote_interrupt_disable(uint32_t mask)
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{
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nrf_gpiote_int_disable(mask);
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}
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/* Clear GPIOTE Port Event */
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void nrf_gpiote_clear_port_event(void)
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{
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NRF_GPIOTE->EVENTS_PORT = 0;
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}
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/* Initialization for GPIO Port 0 */
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#ifdef CONFIG_GPIO_NRF5_P0
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static int gpio_nrf5_P0_init(struct device *dev)
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{
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gpio_nrf5_init(dev);
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return 0;
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}
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static const struct gpio_nrf5_config gpio_nrf5_P0_cfg = {
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.gpio_base_addr = NRF_GPIO_BASE,
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.gpio_port = 0,
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};
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static struct gpio_nrf5_data gpio_data_P0;
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DEVICE_AND_API_INIT(gpio_nrf5_P0, CONFIG_GPIO_NRF5_P0_DEV_NAME, gpio_nrf5_P0_init,
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&gpio_data_P0, &gpio_nrf5_P0_cfg,
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POST_KERNEL, CONFIG_GPIO_NRF5_INIT_PRIORITY,
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&gpio_nrf5_drv_api_funcs);
|
|
|
|
#endif /* CONFIG_GPIO_NRF5_P0 */
|
|
|
|
/* Initialization for GPIO Port 1 */
|
|
#if defined(CONFIG_GPIO_NRF5_P1)
|
|
static int gpio_nrf5_P1_init(struct device *dev)
|
|
{
|
|
#if !defined(CONFIG_GPIO_NRF5_P0)
|
|
gpio_nrf5_init(dev);
|
|
#endif /* CONFIG_GPIO_NRF5_P0 */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct gpio_nrf5_config gpio_nrf5_P1_cfg = {
|
|
.gpio_base_addr = NRF_P1_BASE,
|
|
.gpio_port = 1,
|
|
};
|
|
|
|
static struct gpio_nrf5_data gpio_data_P1;
|
|
|
|
|
|
DEVICE_AND_API_INIT(gpio_nrf5_P1, CONFIG_GPIO_NRF5_P1_DEV_NAME,
|
|
gpio_nrf5_P1_init, &gpio_data_P1, &gpio_nrf5_P1_cfg,
|
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
&gpio_nrf5_drv_api_funcs);
|
|
|
|
#endif /* CONFIG_GPIO_NRF5_P1 */
|