Bhavesh Bhojwani 3ec1caa504 dts/arm: st: g0: closes parenthesis for soc ... This commit adds a closing parenthesis for soc model of stm32g050. Resolves issue #36014 Signed-off-by: Bhavesh Bhojwani <bhaavesh.bhojwaani@gmail.com>		2021-06-08 14:36:27 -05:00
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arc
arm	dts/arm: st: g0: closes parenthesis for soc	2021-06-08 14:36:27 -05:00
arm64
bindings	dts: arm: nxp: Add port property to nxp,lpc-gpio nodes	2021-05-31 17:45:05 +02:00
common	dts/arm: stm32: Add clocks nodes on stm32wb,l4 and stm32f4 series	2021-04-27 11:53:37 +02:00
nios2	nios2: max10: fix uart0 base register	2021-05-26 18:09:47 -05:00
posix
riscv	dts: riscv: it8xxx2: fix default status of UART	2021-05-12 13:01:56 -05:00
sparc
x86	drivers: gpio: Add GPIO driver for Intel Elkhart Lake	2021-05-07 09:45:50 -04:00
xtensa
binding-template.yaml
Kconfig