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https://github.com/zephyrproject-rtos/zephyr
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MAX32657 is Cortex-M33 based Analog Devices MCU. It supports ARM TrustZone security model. There will be two boards of this MCU Secure and Non-Secure This commit defines Secure version of peripherals. Basic feature of MAX32657 device: - Core is Cortex-M33 - 50MHz IPO clock - There are 54 interrupt vectors - 1MB flash & 256 SRAM - MAX32657 has: - 1 x UART - 1 x I2C/I3C - 1 x SPI - 6 x TIMER - 1 x RTC - 1 x WDT - 1 x TRNG Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
72 lines
1.7 KiB
Plaintext
72 lines
1.7 KiB
Plaintext
# Analog Devices MAX32xxx MCU family
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# Copyright (c) 2023-2025 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_MAX32
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select CLOCK_CONTROL
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select BUILD_OUTPUT_HEX
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select SOC_EARLY_INIT_HOOK
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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config SOC_FAMILY_MAX32_M33
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select ARM
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select CLOCK_CONTROL
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select CPU_CORTEX_M33
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select ARM_TRUSTZONE_M
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select CPU_HAS_ARM_SAU
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select ARMV8_M_DSP
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config SOC_FAMILY_MAX32_M4
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select ARM
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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config SOC_MAX32655_M4
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select MAX32_HAS_SECONDARY_RV32
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config SOC_MAX32680_M4
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select MAX32_HAS_SECONDARY_RV32
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config SOC_MAX32690_M4
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select MAX32_HAS_SECONDARY_RV32
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config SOC_MAX78000_M4
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select MAX32_HAS_SECONDARY_RV32
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config SOC_MAX78002_M4
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select MAX32_HAS_SECONDARY_RV32
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if SOC_FAMILY_MAX32
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config MAX32_ON_ENTER_CPU_IDLE_HOOK
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bool "CPU idle hook enable"
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default y
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imply ARM_ON_ENTER_CPU_IDLE_HOOK
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help
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Enables a hook (z_arm_on_enter_cpu_idle()) that is called when
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the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
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If needed, this hook can be used to prevent the CPU from actually
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entering sleep by skipping the WFE/WFI instruction.
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config MAX32_HAS_SECONDARY_RV32
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bool
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config MAX32_SECONDARY_RV32
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bool "Secondary RISC-V core enable"
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depends on MAX32_HAS_SECONDARY_RV32
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DT_CHOSEN_Z_CODE_RV32_PARTITION := zephyr,code-rv32-partition
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config MAX32_SECONDARY_RV32_BOOT_ADDRESS
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hex "Secondary RISC-V core boot address"
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_RV32_PARTITION))
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depends on MAX32_SECONDARY_RV32
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endif # SOC_FAMILY_MAX32
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