mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 04:24:57 +00:00
ab06ec63f9
Add mutex to lock STM32 I2C bus in order to guarantee that data transfers are atomic and have exclusive access to the bus. Issue has been found fetching data from multiple sensors on I2C bus in a mixed context of thread and triggered interrupt. Signed-off-by: Armando Visconti <armando.visconti@st.com>
410 lines
10 KiB
C
410 lines
10 KiB
C
/*
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* Copyright (c) 2016 BayLibre, SAS
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* Copyright (c) 2017 Linaro Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <clock_control/stm32_clock_control.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <kernel.h>
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#include <soc.h>
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#include <errno.h>
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#include <i2c.h>
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#include "i2c_ll_stm32.h"
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(i2c_ll_stm32);
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#include "i2c-priv.h"
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int i2c_stm32_runtime_configure(struct device *dev, u32_t config)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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u32_t clock = 0U;
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int ret;
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#if defined(CONFIG_SOC_SERIES_STM32F3X) || defined(CONFIG_SOC_SERIES_STM32F0X)
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LL_RCC_ClocksTypeDef rcc_clocks;
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/*
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* STM32F0/3 I2C's independent clock source supports only
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* HSI and SYSCLK, not APB1. We force clock variable to
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* SYSCLK frequency.
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*/
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LL_RCC_GetSystemClocksFreq(&rcc_clocks);
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clock = rcc_clocks.SYSCLK_Frequency;
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#else
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clock_control_get_rate(device_get_binding(STM32_CLOCK_CONTROL_NAME),
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(clock_control_subsys_t *) &cfg->pclken, &clock);
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#endif /* CONFIG_SOC_SERIES_STM32F3X) || CONFIG_SOC_SERIES_STM32F0X */
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data->dev_config = config;
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k_sem_take(&data->bus_mutex, K_FOREVER);
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LL_I2C_Disable(i2c);
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LL_I2C_SetMode(i2c, LL_I2C_MODE_I2C);
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ret = stm32_i2c_configure_timing(dev, clock);
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k_sem_give(&data->bus_mutex);
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return ret;
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}
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#define OPERATION(msg) (((struct i2c_msg *) msg)->flags & I2C_MSG_RW_MASK)
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static int i2c_stm32_transfer(struct device *dev, struct i2c_msg *msg,
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u8_t num_msgs, u16_t slave)
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{
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struct i2c_stm32_data *data = DEV_DATA(dev);
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#if defined(CONFIG_I2C_STM32_V1)
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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#endif
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struct i2c_msg *current, *next;
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int ret = 0;
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/* Check for validity of all messages, to prevent having to abort
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* in the middle of a transfer
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*/
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current = msg;
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/*
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* Set I2C_MSG_RESTART flag on first message in order to send start
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* condition
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*/
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current->flags |= I2C_MSG_RESTART;
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for (u8_t i = 1; i <= num_msgs; i++) {
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/* Maximum length of a single message is 255 Bytes */
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if (current->len > 255) {
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ret = -EINVAL;
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break;
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}
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if (i < num_msgs) {
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next = current + 1;
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/*
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* Restart condition between messages
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* of different directions is required
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*/
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if (OPERATION(current) != OPERATION(next)) {
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if (!(next->flags & I2C_MSG_RESTART)) {
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ret = -EINVAL;
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break;
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}
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}
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/* Stop condition is only allowed on last message */
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if (current->flags & I2C_MSG_STOP) {
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ret = -EINVAL;
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break;
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}
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} else {
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/* Stop condition is required for the last message */
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current->flags |= I2C_MSG_STOP;
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}
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current++;
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}
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if (ret) {
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return ret;
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}
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/* Send out messages */
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k_sem_take(&data->bus_mutex, K_FOREVER);
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#if defined(CONFIG_I2C_STM32_V1)
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LL_I2C_Enable(i2c);
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#endif
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current = msg;
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while (num_msgs > 0) {
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u8_t *next_msg_flags = NULL;
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if (num_msgs > 1) {
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next = current + 1;
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next_msg_flags = &(next->flags);
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}
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if ((current->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
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ret = stm32_i2c_msg_write(dev, current, next_msg_flags,
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slave);
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} else {
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ret = stm32_i2c_msg_read(dev, current, next_msg_flags,
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slave);
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}
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if (ret < 0) {
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break;
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}
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current++;
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num_msgs--;
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}
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#if defined(CONFIG_I2C_STM32_V1)
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LL_I2C_Disable(i2c);
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#endif
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k_sem_give(&data->bus_mutex);
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return ret;
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}
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static const struct i2c_driver_api api_funcs = {
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.configure = i2c_stm32_runtime_configure,
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.transfer = i2c_stm32_transfer,
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#if defined(CONFIG_I2C_SLAVE) && defined(CONFIG_I2C_STM32_V2)
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.slave_register = i2c_stm32_slave_register,
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.slave_unregister = i2c_stm32_slave_unregister,
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#endif
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};
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static int i2c_stm32_init(struct device *dev)
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{
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struct device *clock = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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u32_t bitrate_cfg;
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int ret;
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struct i2c_stm32_data *data = DEV_DATA(dev);
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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k_sem_init(&data->device_sync_sem, 0, UINT_MAX);
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cfg->irq_config_func(dev);
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#endif
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/*
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* initialize mutex used when multiple transfers
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* are taking place to guarantee that each one is
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* atomic and has exclusive access to the I2C bus.
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*/
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k_sem_init(&data->bus_mutex, 1, 1);
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__ASSERT_NO_MSG(clock);
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if (clock_control_on(clock,
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(clock_control_subsys_t *) &cfg->pclken) != 0) {
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LOG_ERR("i2c: failure enabling clock");
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return -EIO;
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}
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#if defined(CONFIG_SOC_SERIES_STM32F3X) || defined(CONFIG_SOC_SERIES_STM32F0X)
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/*
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* STM32F0/3 I2C's independent clock source supports only
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* HSI and SYSCLK, not APB1. We force I2C clock source to SYSCLK.
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* I2C2 on STM32F0 uses APB1 clock as I2C clock source
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*/
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switch ((u32_t)cfg->i2c) {
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#ifdef CONFIG_I2C_1
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case DT_I2C_1_BASE_ADDRESS:
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LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_SYSCLK);
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break;
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#endif /* CONFIG_I2C_1 */
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#if defined(CONFIG_SOC_SERIES_STM32F3X) && defined(CONFIG_I2C_2)
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case DT_I2C_2_BASE_ADDRESS:
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LL_RCC_SetI2CClockSource(LL_RCC_I2C2_CLKSOURCE_SYSCLK);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32F3X && CONFIG_I2C_2 */
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#ifdef CONFIG_I2C_3
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case DT_I2C_3_BASE_ADDRESS:
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LL_RCC_SetI2CClockSource(LL_RCC_I2C3_CLKSOURCE_SYSCLK);
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break;
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#endif /* CONFIG_I2C_3 */
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}
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#endif /* CONFIG_SOC_SERIES_STM32F3X) || CONFIG_SOC_SERIES_STM32F0X */
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bitrate_cfg = _i2c_map_dt_bitrate(cfg->bitrate);
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ret = i2c_stm32_runtime_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
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if (ret < 0) {
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LOG_ERR("i2c: failure initializing");
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return ret;
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}
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return 0;
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}
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#ifdef CONFIG_I2C_1
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_1(struct device *port);
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#endif
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static const struct i2c_stm32_config i2c_stm32_cfg_1 = {
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.i2c = (I2C_TypeDef *)DT_I2C_1_BASE_ADDRESS,
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.pclken = {
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.enr = DT_I2C_1_CLOCK_BITS,
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.bus = DT_I2C_1_CLOCK_BUS,
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},
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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.irq_config_func = i2c_stm32_irq_config_func_1,
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#endif
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.bitrate = DT_I2C_1_BITRATE,
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};
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static struct i2c_stm32_data i2c_stm32_dev_data_1;
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DEVICE_AND_API_INIT(i2c_stm32_1, CONFIG_I2C_1_NAME, &i2c_stm32_init,
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&i2c_stm32_dev_data_1, &i2c_stm32_cfg_1,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_1(struct device *dev)
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{
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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IRQ_CONNECT(DT_I2C_1_COMBINED_IRQ, DT_I2C_1_COMBINED_IRQ_PRI,
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stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_1), 0);
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irq_enable(DT_I2C_1_COMBINED_IRQ);
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#else
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IRQ_CONNECT(DT_I2C_1_EVENT_IRQ, DT_I2C_1_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_1), 0);
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irq_enable(DT_I2C_1_EVENT_IRQ);
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IRQ_CONNECT(DT_I2C_1_ERROR_IRQ, DT_I2C_1_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_1), 0);
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irq_enable(DT_I2C_1_ERROR_IRQ);
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#endif
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}
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#endif
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#endif /* CONFIG_I2C_1 */
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#ifdef CONFIG_I2C_2
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_2(struct device *port);
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#endif
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static const struct i2c_stm32_config i2c_stm32_cfg_2 = {
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.i2c = (I2C_TypeDef *)DT_I2C_2_BASE_ADDRESS,
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.pclken = {
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.enr = DT_I2C_2_CLOCK_BITS,
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.bus = DT_I2C_2_CLOCK_BUS,
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},
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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.irq_config_func = i2c_stm32_irq_config_func_2,
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#endif
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.bitrate = DT_I2C_2_BITRATE,
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};
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static struct i2c_stm32_data i2c_stm32_dev_data_2;
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DEVICE_AND_API_INIT(i2c_stm32_2, CONFIG_I2C_2_NAME, &i2c_stm32_init,
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&i2c_stm32_dev_data_2, &i2c_stm32_cfg_2,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_2(struct device *dev)
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{
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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IRQ_CONNECT(DT_I2C_2_COMBINED_IRQ, DT_I2C_2_COMBINED_IRQ_PRI,
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stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_2), 0);
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irq_enable(DT_I2C_2_COMBINED_IRQ);
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#else
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IRQ_CONNECT(DT_I2C_2_EVENT_IRQ, DT_I2C_2_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_2), 0);
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irq_enable(DT_I2C_2_EVENT_IRQ);
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IRQ_CONNECT(DT_I2C_2_ERROR_IRQ, DT_I2C_2_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_2), 0);
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irq_enable(DT_I2C_2_ERROR_IRQ);
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#endif
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}
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#endif
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#endif /* CONFIG_I2C_2 */
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#ifdef CONFIG_I2C_3
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#ifndef I2C3_BASE
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#error "I2C_3 is not available on the platform that you selected"
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#endif /* I2C3_BASE */
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_3(struct device *port);
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#endif
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static const struct i2c_stm32_config i2c_stm32_cfg_3 = {
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.i2c = (I2C_TypeDef *)DT_I2C_3_BASE_ADDRESS,
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.pclken = {
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.enr = DT_I2C_3_CLOCK_BITS,
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.bus = DT_I2C_3_CLOCK_BUS,
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},
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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.irq_config_func = i2c_stm32_irq_config_func_3,
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#endif
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.bitrate = DT_I2C_3_BITRATE,
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};
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static struct i2c_stm32_data i2c_stm32_dev_data_3;
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DEVICE_AND_API_INIT(i2c_stm32_3, CONFIG_I2C_3_NAME, &i2c_stm32_init,
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&i2c_stm32_dev_data_3, &i2c_stm32_cfg_3,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_3(struct device *dev)
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{
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IRQ_CONNECT(DT_I2C_3_EVENT_IRQ, DT_I2C_3_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_3), 0);
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irq_enable(DT_I2C_3_EVENT_IRQ);
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IRQ_CONNECT(DT_I2C_3_ERROR_IRQ, DT_I2C_3_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_3), 0);
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irq_enable(DT_I2C_3_ERROR_IRQ);
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}
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#endif
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#endif /* CONFIG_I2C_3 */
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#ifdef CONFIG_I2C_4
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#ifndef I2C4_BASE
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#error "I2C_4 is not available on the platform that you selected"
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#endif /* I2C4_BASE */
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_4(struct device *port);
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#endif
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static const struct i2c_stm32_config i2c_stm32_cfg_4 = {
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.i2c = (I2C_TypeDef *)DT_I2C_4_BASE_ADDRESS,
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.pclken = {
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.enr = DT_I2C_4_CLOCK_BITS,
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.bus = DT_I2C_4_CLOCK_BUS,
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},
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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.irq_config_func = i2c_stm32_irq_config_func_4,
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#endif
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.bitrate = DT_I2C_4_BITRATE,
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};
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static struct i2c_stm32_data i2c_stm32_dev_data_4;
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DEVICE_AND_API_INIT(i2c_stm32_4, CONFIG_I2C_4_NAME, &i2c_stm32_init,
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&i2c_stm32_dev_data_4, &i2c_stm32_cfg_4,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_4(struct device *dev)
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{
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IRQ_CONNECT(DT_I2C_4_EVENT_IRQ, DT_I2C_4_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_4), 0);
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irq_enable(DT_I2C_4_EVENT_IRQ);
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IRQ_CONNECT(DT_I2C_4_ERROR_IRQ, DT_I2C_4_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_4), 0);
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irq_enable(DT_I2C_4_ERROR_IRQ);
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}
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#endif
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#endif /* CONFIG_I2C_4 */
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