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The Ambiq MSPI controller is implemented using the MSPI bus API. The hardware supports up to 48MHz octal SDR with XIP, scrambling and hardware command queue features. Signed-off-by: Swift Tian <swift.tian@ambiq.com>
29 lines
705 B
Plaintext
29 lines
705 B
Plaintext
# Copyright (c) 2024, Ambiq Micro Inc. <www.ambiq.com>
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# SPDX-License-Identifier: Apache-2.0
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config MSPI_AMBIQ_AP3
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bool "Ambiq Apollo3 series MSPI driver"
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default y
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depends on DT_HAS_AMBIQ_MSPI_CONTROLLER_ENABLED
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select AMBIQ_HAL
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select AMBIQ_HAL_USE_MSPI
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select MSPI_XIP
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select MSPI_SCRAMBLE
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select MSPI_TIMING
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select GPIO
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help
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Enable driver for Ambiq MSPI.
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config MSPI_AMBIQ_BUFF_RAM_LOCATION
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hex "byte offset to SRAM_BASE_ADDRESS"
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default 0x50000
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help
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This option specifies the mspi buffer/heap start address
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config MSPI_AMBIQ_BUFF_ALIGNMENT
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int "byte alignment of the MSPI buffer"
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default 8 if MSPI_AMBIQ_AP3
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default 4
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help
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This option specifies the mspi buffer alignment
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