mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 07:22:28 +00:00
7cef0e3614
Use the device API macro to place the driver API instance into an iterable section. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
406 lines
13 KiB
C
406 lines
13 KiB
C
/*
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc23x0_uart
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#include <zephyr/device.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <errno.h>
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#include <driverlib/uart.h>
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#include <driverlib/clkctl.h>
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struct uart_cc23x0_config {
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uint32_t reg;
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uint32_t sys_clk_freq;
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const struct pinctrl_dev_config *pcfg;
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};
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struct uart_cc23x0_data {
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struct uart_config uart_config;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t callback;
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void *user_data;
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static int uart_cc23x0_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_cc23x0_config *config = dev->config;
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if (!UARTCharAvailable(config->reg)) {
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return -1;
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}
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*c = UARTGetCharNonBlocking(config->reg);
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return 0;
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}
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static void uart_cc23x0_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_cc23x0_config *config = dev->config;
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UARTPutChar(config->reg, c);
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}
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static int uart_cc23x0_err_check(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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uint32_t flags = UARTGetRxError(config->reg);
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int error = 0;
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error |= (flags & UART_RXERROR_FRAMING) ? UART_ERROR_FRAMING : 0;
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error |= (flags & UART_RXERROR_PARITY) ? UART_ERROR_PARITY : 0;
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error |= (flags & UART_RXERROR_BREAK) ? UART_BREAK : 0;
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error |= (flags & UART_RXERROR_OVERRUN) ? UART_ERROR_OVERRUN : 0;
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UARTClearRxError(config->reg);
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return error;
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}
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static int uart_cc23x0_configure(const struct device *dev, const struct uart_config *cfg)
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{
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const struct uart_cc23x0_config *config = dev->config;
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struct uart_cc23x0_data *data = dev->data;
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uint32_t line_ctrl = 0;
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bool flow_ctrl;
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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line_ctrl |= UART_CONFIG_PAR_NONE;
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break;
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case UART_CFG_PARITY_ODD:
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line_ctrl |= UART_CONFIG_PAR_ODD;
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break;
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case UART_CFG_PARITY_EVEN:
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line_ctrl |= UART_CONFIG_PAR_EVEN;
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break;
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case UART_CFG_PARITY_MARK:
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line_ctrl |= UART_CONFIG_PAR_ONE;
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break;
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case UART_CFG_PARITY_SPACE:
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line_ctrl |= UART_CONFIG_PAR_ZERO;
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break;
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default:
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return -EINVAL;
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}
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switch (cfg->stop_bits) {
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case UART_CFG_STOP_BITS_1:
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line_ctrl |= UART_CONFIG_STOP_ONE;
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break;
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case UART_CFG_STOP_BITS_2:
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line_ctrl |= UART_CONFIG_STOP_TWO;
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break;
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case UART_CFG_STOP_BITS_0_5:
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case UART_CFG_STOP_BITS_1_5:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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switch (cfg->data_bits) {
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case UART_CFG_DATA_BITS_5:
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line_ctrl |= UART_CONFIG_WLEN_5;
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break;
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case UART_CFG_DATA_BITS_6:
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line_ctrl |= UART_CONFIG_WLEN_6;
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break;
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case UART_CFG_DATA_BITS_7:
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line_ctrl |= UART_CONFIG_WLEN_7;
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break;
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case UART_CFG_DATA_BITS_8:
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line_ctrl |= UART_CONFIG_WLEN_8;
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break;
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default:
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return -EINVAL;
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}
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switch (cfg->flow_ctrl) {
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case UART_CFG_FLOW_CTRL_NONE:
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flow_ctrl = false;
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break;
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case UART_CFG_FLOW_CTRL_RTS_CTS:
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flow_ctrl = true;
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break;
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case UART_CFG_FLOW_CTRL_DTR_DSR:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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/* Disables UART before setting control registers */
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UARTConfigSetExpClk(config->reg, config->sys_clk_freq, cfg->baudrate, line_ctrl);
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if (flow_ctrl) {
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UARTEnableCTS(config->reg);
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UARTEnableRTS(config->reg);
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} else {
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UARTDisableCTS(config->reg);
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UARTDisableRTS(config->reg);
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}
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/* Re-enable UART */
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UARTEnable(config->reg);
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/* Make use of the FIFO to reduce chances of data being lost */
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UARTEnableFifo(config->reg);
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data->uart_config = *cfg;
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return 0;
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}
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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static int uart_cc23x0_config_get(const struct device *dev, struct uart_config *cfg)
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{
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const struct uart_cc23x0_data *data = dev->data;
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*cfg = data->uart_config;
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_cc23x0_fifo_fill(const struct device *dev, const uint8_t *buf, int len)
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{
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const struct uart_cc23x0_config *config = dev->config;
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int n = 0;
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while (n < len) {
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if (!UARTSpaceAvailable(config->reg)) {
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break;
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}
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UARTPutCharNonBlocking(config->reg, buf[n]);
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n++;
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}
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return n;
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}
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static int uart_cc23x0_fifo_read(const struct device *dev, uint8_t *buf, const int len)
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{
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const struct uart_cc23x0_config *config = dev->config;
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int c, n;
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n = 0;
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while (n < len) {
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if (!UARTCharAvailable(config->reg)) {
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break;
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}
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c = UARTGetCharNonBlocking(config->reg);
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buf[n++] = c;
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}
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return n;
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}
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static void uart_cc23x0_irq_tx_enable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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UARTEnableInt(config->reg, UART_INT_TX);
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}
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static void uart_cc23x0_irq_tx_disable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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UARTDisableInt(config->reg, UART_INT_TX);
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}
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static int uart_cc23x0_irq_tx_ready(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTSpaceAvailable(config->reg) ? 1 : 0;
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}
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static void uart_cc23x0_irq_rx_enable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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/* Trigger the ISR on both RX and Receive Timeout. This is to allow
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* the use of the hardware FIFOs for more efficient operation
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*/
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UARTEnableInt(config->reg, UART_INT_RX | UART_INT_RT);
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}
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static void uart_cc23x0_irq_rx_disable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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UARTDisableInt(config->reg, UART_INT_RX | UART_INT_RT);
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}
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static int uart_cc23x0_irq_tx_complete(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTBusy(config->reg) ? 0 : 1;
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}
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static int uart_cc23x0_irq_rx_ready(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTCharAvailable(config->reg) ? 1 : 0;
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}
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static void uart_cc23x0_irq_err_enable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTEnableInt(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE);
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}
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static void uart_cc23x0_irq_err_disable(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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return UARTDisableInt(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE);
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}
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static int uart_cc23x0_irq_is_pending(const struct device *dev)
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{
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const struct uart_cc23x0_config *config = dev->config;
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/* Read masked interrupt status */
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uint32_t status = UARTIntStatus(config->reg, true);
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return status ? 1 : 0;
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}
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static int uart_cc23x0_irq_update(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 1;
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}
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static void uart_cc23x0_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
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void *user_data)
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{
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struct uart_cc23x0_data *data = dev->data;
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data->callback = cb;
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data->user_data = user_data;
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}
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static void uart_cc23x0_isr(const struct device *dev)
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{
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struct uart_cc23x0_data *data = dev->data;
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if (data->callback) {
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data->callback(dev, data->user_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static DEVICE_API(uart, uart_cc23x0_driver_api) = {
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.poll_in = uart_cc23x0_poll_in,
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.poll_out = uart_cc23x0_poll_out,
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.err_check = uart_cc23x0_err_check,
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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.configure = uart_cc23x0_configure,
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.config_get = uart_cc23x0_config_get,
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#endif
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_cc23x0_fifo_fill,
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.fifo_read = uart_cc23x0_fifo_read,
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.irq_tx_enable = uart_cc23x0_irq_tx_enable,
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.irq_tx_disable = uart_cc23x0_irq_tx_disable,
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.irq_tx_ready = uart_cc23x0_irq_tx_ready,
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.irq_rx_enable = uart_cc23x0_irq_rx_enable,
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.irq_rx_disable = uart_cc23x0_irq_rx_disable,
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.irq_tx_complete = uart_cc23x0_irq_tx_complete,
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.irq_rx_ready = uart_cc23x0_irq_rx_ready,
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.irq_err_enable = uart_cc23x0_irq_err_enable,
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.irq_err_disable = uart_cc23x0_irq_err_disable,
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.irq_is_pending = uart_cc23x0_irq_is_pending,
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.irq_update = uart_cc23x0_irq_update,
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.irq_callback_set = uart_cc23x0_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define UART_CC23X0_IRQ_CFG(n) \
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do { \
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UARTClearInt(config->reg, UART_INT_RX); \
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UARTClearInt(config->reg, UART_INT_RT); \
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\
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), uart_cc23x0_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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} while (false)
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#define UART_CC23X0_INT_FIELDS .callback = NULL, .user_data = NULL,
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#else
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#define UART_CC23X0_IRQ_CFG(n)
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#define UART_CC23X0_INT_FIELDS
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#define UART_CC23X0_DEVICE_DEFINE(n) \
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\
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DEVICE_DT_INST_DEFINE(n, uart_cc23x0_init_##n, NULL, &uart_cc23x0_data_##n, \
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&uart_cc23x0_config_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
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&uart_cc23x0_driver_api)
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#define UART_CC23X0_INIT_FUNC(n) \
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static int uart_cc23x0_init_##n(const struct device *dev) \
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{ \
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const struct uart_cc23x0_config *config = dev->config; \
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struct uart_cc23x0_data *data = dev->data; \
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int ret; \
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\
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CLKCTLEnable(CLKCTL_BASE, CLKCTL_UART0); \
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\
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); \
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if (ret < 0) { \
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return ret; \
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} \
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\
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/* Configure and enable UART */ \
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ret = uart_cc23x0_configure(dev, &data->uart_config); \
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\
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/* Enable interrupts */ \
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UART_CC23X0_IRQ_CFG(n); \
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\
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return ret; \
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}
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#define UART_CC23X0_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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UART_CC23X0_INIT_FUNC(n); \
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\
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static struct uart_cc23x0_config uart_cc23x0_config_##n = { \
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.reg = DT_INST_REG_ADDR(n), \
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.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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}; \
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\
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static struct uart_cc23x0_data uart_cc23x0_data_##n = { \
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.uart_config = \
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{ \
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.baudrate = DT_INST_PROP(n, current_speed), \
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.parity = DT_INST_ENUM_IDX(n, parity), \
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.stop_bits = DT_INST_ENUM_IDX(n, stop_bits), \
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.data_bits = DT_INST_ENUM_IDX(n, data_bits), \
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.flow_ctrl = DT_INST_PROP(n, hw_flow_control), \
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}, \
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UART_CC23X0_INT_FIELDS \
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}; \
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UART_CC23X0_DEVICE_DEFINE(n);
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DT_INST_FOREACH_STATUS_OKAY(UART_CC23X0_INIT)
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