mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-27 22:05:21 +00:00
bb19e6f82f
Changed names of Kconfig flags, variables, functions, files and return codes consistent with names used in the RFC. Updated relevant comments to match the changes. Origin: Original Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8 Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
417 lines
11 KiB
ArmAsm
417 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2010-2015 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Crt0 module for the IA-32 boards
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*
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* This module contains the initial code executed by the Zephyr Kernel ELF image
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* after having been loaded into RAM.
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*/
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#define _ASMLANGUAGE
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#include <arch/x86/asm.h>
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/* exports (private APIs) */
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GTEXT(__start)
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/* externs */
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GTEXT(_Cstart)
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GDATA(_idt_base_address)
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GDATA(_interrupt_stack)
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GDATA(_Idt)
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#ifndef CONFIG_GDT_DYNAMIC
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GDATA(_gdt)
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#endif
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#if defined(CONFIG_SSE)
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GDATA(_sse_mxcsr_default_value)
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#endif
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#if defined(CONFIG_BOOT_TIME_MEASUREMENT)
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GDATA(__start_tsc)
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#endif
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#ifdef CONFIG_SYS_POWER_DEEP_SLEEP
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GDATA(_sys_soc_resume)
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#endif
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/* processor is executing in 32-bit protected mode */
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.balign 16,0x90
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SECTION_FUNC(TEXT_START, __start)
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#ifdef CONFIG_BOOT_TIME_MEASUREMENT
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/*
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* Record BootTime from start of Kernel.
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* Store value temporarily in Register edi & esi and
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* write to memory once memory access is allowed.
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* That is, once the data segment register has been setup to access
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* the .data/.rodata/.bss section of the linked image.
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*/
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rdtsc
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mov %eax, %esi /* low value */
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mov %edx, %edi /* high value */
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#endif
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/* Enable write-back caching by clearing the NW and CD bits */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/*
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* Ensure interrupts are disabled. Interrupts are enabled when
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* the first context switch occurs.
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*/
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cli
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/*
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* Although the bootloader sets up an Interrupt Descriptor Table (IDT)
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* and a Global Descriptor Table (GDT), the specification encourages
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* booted operating systems to setup their own IDT and GDT.
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*/
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lgdt _gdt_rom /* load 32-bit operand size GDT */
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lidt _Idt /* load 32-bit operand size IDT */
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#ifdef CONFIG_BOOTLOADER_UNKNOWN
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/*
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* Where we do not do the protected mode switch and the
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* bootloader is unknown, do not make the assumption that the segment
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* registers are set correctly.
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*
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* This is a special case for the ia32 platform, which must work for
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* multiple platforms (QEMU, generic PC board, etc.). With other
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* platforms the bootloader is well known so assumptions can be made.
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*/
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movw $0x10, %ax /* data segment selector (entry = 3) */
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movw %ax, %ds /* set DS */
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movw %ax, %es /* set ES */
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movw %ax, %fs /* set FS */
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movw %ax, %gs /* set GS */
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movw %ax, %ss /* set SS */
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ljmp $0x08, $__csSet /* set CS = 0x08 */
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__csSet:
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#endif /* CONFIG_BOOTLOADER_UNKNOWN */
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#ifdef CONFIG_BOOT_TIME_MEASUREMENT
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/*
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* Store rdtsc result from temporary regiter ESI & EDI into memory.
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*/
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mov %esi, __start_tsc /* low value */
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mov %edi, __start_tsc+4 /* high value */
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#endif
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#if !defined(CONFIG_FLOAT)
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/*
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* Force an #NM exception for floating point instructions
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* since FP support hasn't been configured
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*/
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movl %cr0, %eax /* move CR0 to EAX */
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orl $0x2e, %eax /* CR0[NE+TS+EM+MP]=1 */
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movl %eax, %cr0 /* move EAX to CR0 */
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#else
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/*
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* Permit use of x87 FPU instructions
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*
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* Note that all floating point exceptions are masked by default,
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* and that _no_ handler for x87 FPU exceptions (#MF) is provided.
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*/
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movl %cr0, %eax /* move CR0 to EAX */
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orl $0x22, %eax /* CR0[NE+MP]=1 */
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andl $~0xc, %eax /* CR0[TS+EM]=0 */
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movl %eax, %cr0 /* move EAX to CR0 */
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fninit /* set x87 FPU to its default state */
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#if defined(CONFIG_SSE)
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/*
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* Permit use of SSE instructions
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*
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* Note that all SSE exceptions are masked by default,
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* and that _no_ handler for SSE exceptions (#XM) is provided.
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*/
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movl %cr4, %eax /* move CR4 to EAX */
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orl $0x200, %eax /* CR4[OSFXSR] = 1 */
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andl $~0x400, %eax /* CR4[OSXMMEXCPT] = 0 */
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movl %eax, %cr4 /* move EAX to CR4 */
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ldmxcsr _sse_mxcsr_default_value /* initialize SSE control/status reg */
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#endif /* CONFIG_SSE */
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#endif /* !CONFIG_FLOAT */
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/*
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* Set the stack pointer to the area used for the interrupt stack.
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* Note this stack is used during the execution of __start() and
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* _Cstart() until the multi-tasking kernel is initialized. The
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* dual-purposing of this area of memory is safe since
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* interrupts are disabled until the first context switch.
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*
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* This is also used to call the _sys_soc_resume() routine
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* to avoid memory corruption if the system is resuming from
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* deep sleep. It is important that _sys_soc_resume() restores
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* the stack pointer to what it was at deep sleep before
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* enabling interrupts. This is necessary to avoid
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* interfering with interrupt handler use of this stack.
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* If it is a cold boot then _sys_soc_resume() should not do
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* anything and must return immediately.
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*/
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movl $_interrupt_stack, %esp
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addl $CONFIG_ISR_STACK_SIZE, %esp
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/* align to stack boundary: ROUND_DOWN (%esp, 4) */
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andl $0xfffffffc, %esp
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#ifdef CONFIG_SYS_POWER_DEEP_SLEEP
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/*
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* Invoke _sys_soc_resume() hook to handle resume from deep sleep.
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* It should first check whether system is recovering from
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* deep sleep state. If it is, then this function should restore
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* states and resume at the point system went to deep sleep.
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* In this case this function will never return.
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*
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* If system is not recovering from deep sleep then it is a
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* cold boot. In this case, this function would immediately
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* return and execution falls through to cold boot path.
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*/
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call _sys_soc_resume
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#endif
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#ifdef CONFIG_XIP
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/*
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* copy DATA section from ROM to RAM region
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* DATA is followed by BSS section.
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* Given that BSS section is initialized after this copy, we can
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* safely over-write into the next section.
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* Note: __data_num_words is a multiple of 4 bytes
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* rounded up to next 4 bytes.
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* Note: the sections might not be 4 byte aligned.
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*/
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movl $__data_ram_start, %edi /* DATA in RAM (dest) */
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movl $__data_rom_start, %esi /* DATA in ROM (src) */
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movl $__data_num_words, %ecx /* Size of DATA in quad bytes */
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je copyDataDone
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#ifdef CONFIG_SSE
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/* copy 16 bytes at a time using XMM until < 16 bytes remain */
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movl %ecx ,%edx /* save number of quad bytes */
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shrl $2, %ecx /* How many 16 bytes? */
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je dataWords
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dataDQ:
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movdqu (%esi), %xmm0
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movdqu %xmm0, (%edi)
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addl $16, %esi
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addl $16, %edi
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loop dataDQ
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dataWords:
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movl %edx, %ecx /* restore # quad bytes */
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andl $0x3, %ecx /* only need to copy at most 3 quad bytes */
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#endif /* CONFIG_SSE */
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rep
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movsl /* copy data 4 bytes at a time */
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copyDataDone:
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#endif /* CONFIG_XIP */
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/*
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* Clear BSS: bzero (__bss_start, __bss_num_words*4)
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*
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* It's assumed that BSS size will be a multiple of a long (4 bytes),
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* and aligned on a double word (32-bit) boundary
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*/
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#ifdef CONFIG_SSE
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/* use XMM register to clear 16 bytes at a time */
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pxor %xmm0, %xmm0 /* zero out xmm0 register */
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movl $__bss_start, %edi /* load BSS start address */
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movl $__bss_num_words, %ecx /* number of quad bytes in .bss */
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movl %ecx, %edx /* make a copy of # quad bytes */
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shrl $2, %ecx /* How many multiples of 16 byte ? */
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je bssWords
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bssDQ:
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movdqu %xmm0, (%edi) /* zero 16 bytes... */
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addl $16, %edi
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loop bssDQ
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/* fall through to handle the remaining double words (32-bit chunks) */
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bssWords:
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xorl %eax, %eax /* fill memory with 0 */
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movl %edx, %ecx /* move # quad bytes into ECX (for rep) */
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andl $0x3, %ecx /* only need to zero at most 3 quad bytes */
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cld
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rep
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stosl /* zero memory per 4 bytes */
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#else /* !CONFIG_SSE */
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/* clear out BSS double words (32-bits at a time) */
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xorl %eax, %eax /* fill memory with 0 */
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movl $__bss_start, %edi /* load BSS start address */
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movl $__bss_num_words, %ecx /* number of quad bytes */
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cld
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rep
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stosl /* zero memory per 4 bytes */
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#endif /* CONFIG_SSE */
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#ifdef CONFIG_GDT_DYNAMIC
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/* activate RAM-based Global Descriptor Table (GDT) */
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lgdt %ds:_gdt
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#endif
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/* Jump to C portion of kernel initialization and never return */
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jmp _Cstart
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#if defined(CONFIG_SSE)
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/* SSE control & status register initial value */
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_sse_mxcsr_default_value:
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.long 0x1f80 /* all SSE exceptions clear & masked */
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#endif /* CONFIG_SSE */
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/* Interrupt Descriptor Table (IDT) definition */
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_Idt:
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.word (CONFIG_IDT_NUM_VECTORS * 8) - 1 /* limit: size of IDT-1 */
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/*
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* Physical start address = 0. When executing natively, this
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* will be placed at the same location as the interrupt vector table
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* setup by the BIOS (or GRUB?).
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*/
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.long _idt_base_address /* physical start address */
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#ifdef CONFIG_BOOTLOADER_UNKNOWN
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/* Multiboot header definition is needed for some bootloaders */
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/*
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* The multiboot header must be in the first 8 Kb of the kernel image
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* (not including the ELF section header(s)) and be aligned on a
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* 4 byte boundary.
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*/
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.balign 4,0x90
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.long 0x1BADB002 /* multiboot magic number */
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/*
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* Flags = no bits are being set, specifically bit 16 is not being
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* set since the supplied kernel image is an ELF file, and the
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* multiboot loader shall use the information from the program and
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* section header to load and boot the kernel image.
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*/
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.long 0x00000000
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/*
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* checksum = 32-bit unsigned value which, when added to the other
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* magic fields (i.e. "magic" and "flags"), must have a 32-bit
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* unsigned sum of zero.
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*/
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.long -(0x1BADB002 + 0)
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#endif /* CONFIG_BOOTLOADER_UNKNOWN */
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#ifndef CONFIG_GDT_DYNAMIC
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_gdt:
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#endif
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_gdt_rom:
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.word _gdt_rom_end - _gdt_rom_entries - 1 /* Limit on GDT */
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.long _gdt_rom_entries /* table address: _gdt_rom_entries */
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.balign 16,0x90
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/*
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* The following 3 GDT entries implement the so-called "basic
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* flat model", i.e. a single code segment descriptor and a single
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* data segment descriptor, giving the kernel access to a continuous,
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* unsegmented address space. Both segment descriptors map the entire
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* linear address space (i.e. 0 to 4 GB-1), thus the segmentation
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* mechanism will never generate "out of limit memory reference"
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* exceptions even if physical memory does not reside at the referenced
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* address.
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*
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* The 'A' (accessed) bit in the type field is _not_ set for all the
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* data/code segment descriptors to accommodate placing these entries
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* in ROM, since such use is not planned for this platform.
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*/
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_gdt_rom_entries:
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/* Entry 0 (selector=0x0000): The "NULL descriptor" */
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.word 0x0000
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.word 0x0000
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.byte 0x00
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.byte 0x00
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.byte 0x00
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.byte 0x00
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/* Entry 1 (selector=0x0008): Code descriptor: DPL0 */
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.word 0xffff /* limit: xffff */
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.word 0x0000 /* base : xxxx0000 */
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.byte 0x00 /* base : xx00xxxx */
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.byte 0x9a /* Code e/r, Present, DPL0 */
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.byte 0xcf /* limit: fxxxx, Page Gra, 32bit */
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.byte 0x00 /* base : 00xxxxxx */
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/* Entry 2 (selector=0x0010): Data descriptor: DPL0 */
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.word 0xffff /* limit: xffff */
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.word 0x0000 /* base : xxxx0000 */
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.byte 0x00 /* base : xx00xxxx */
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.byte 0x92 /* Data r/w, Present, DPL0 */
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.byte 0xcf /* limit: fxxxx, Page Gra, 32bit */
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.byte 0x00 /* base : 00xxxxxx */
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_gdt_rom_end:
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