Andy Ross 285c5b26dd xtensa/asm2: Save shift/loop registers on exception entry ... This was a little embarassing. The swap code got this right, and the interrupt exit path got it right, but on entry we weren't ever saving the shift and loop registers for the interrupted context. This almost always worked anyway as the loop registers aren't ever used in any Zephyr code (gcc won't generate this style of loop AFAICT) and the SAR shift amount register is generally used only in two pairs of adjacent instructions making the chance of hitting that exact cycle quite low in general. But of course we have shift-happy crypto code in our tests, so this got caught, thankfully. See https://github.com/zephyrproject-rtos/zephyr/issues/6470 Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2018-03-06 14:13:56 -08:00
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arc
arm	arch: arm: remove redundant dependence on ARM_CORE_MPU	2018-03-06 08:36:34 -05:00
common
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xtensa	xtensa/asm2: Save shift/loop registers on exception entry	2018-03-06 14:13:56 -08:00
CMakeLists.txt
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